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vsia

  • openmore/openmore vsia 评估程序、电子表格说媒文件

    openmore/openmore vsia 评估程序、电子表格说媒文件

    标签: openmore vsia 程序 电子表格

    上传时间: 2014-01-25

    上传用户:xc216

  • 数字集成电路与嵌入式内核系统可测试性设计(影印版)

    ·书中包括的索引使你能够根据自己的需要,直接阅读你所关注的内容。主要内容包括:设计核心,关注嵌入核心和嵌入存储器;系统集成和超大规模集成电路的设计问题;AC扫描、正常速度扫描和嵌入式可测试性设计;内建、自测试、含内存BIST、逻辑BIST及扫描BIST;虚拟测试套接字和隔离测试 ·重用设计,包括重用和隔离测试;用vsia和IEEE P1500标准处理测试问题。 书中穿插的整幅图解直接来自作者的教学材

    标签: 数字集成电路 嵌入式 内核

    上传时间: 2013-04-24

    上传用户:sjb555

  • SOC验证方法

    Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the vsia Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.

    标签: SOC 验证方法

    上传时间: 2014-01-24

    上传用户:xinhaoshan2016

  • SOC验证方法

    Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the vsia Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.

    标签: SOC 验证方法

    上传时间: 2013-11-19

    上传用户:m62383408