this is the documentation for intel processors, first volume. it contains detailed specification and instrucion set - for hardcore programers on assembly
标签： documentation specification processors contains
上传时间： 2017-06-05
上传用户：希酱大魔王
the second volume for intel processor documentation it continues first volume with more processor acces code and specs
标签： processor volume documentation continues
上传时间： 2017-06-05
上传用户：stewart·
PT2322 6 Channel volume Control IC DATASHEET
标签： DATASHEET Channel Control volume
上传时间： 2017-06-08
上传用户：evil
TMS320C54x DSP Reference Set volume 2: Mnemonic Instruction Set
标签： Instruction Reference Set Mnemonic
上传时间： 2017-06-17
上传用户：zhangliming420
Symbian OS C++ for Mobile Phones volume 2
标签： Symbian Mobile Phones volume
上传时间： 2017-06-21
上传用户：koulian
This volume presents the state of the art concerning quality and interestingness measures for data mining. The book summarizes recent developments and presents original research on this topic. The chapters include surveys, comparative studies of existing measures, proposals of new measures, simulations, and case studies. Both theoretical and applied chapters are included. Papers for this book were selected and reviewed for correctness and completeness by an international review committee.
标签： interestingness concerning the presents
上传时间： 2014-01-19
上传用户：ve3344
Thinking in C++ 2nd edition volume 2: STL
标签： Thinking edition volume 2nd
上传时间： 2013-12-22
上传用户：saharawalker
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
标签： technology 2.0 USB designed
上传时间： 2014-01-02
上传用户：二驱蚊器
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
标签： technology 2.0 USB designed
上传时间： 2017-07-05
上传用户：zhoujunzhen
volume of fluid方法中的一种FCT方法的源代码
上传时间： 2017-07-07
上传用户：jing911003
