此曼彻斯特码的解码程序是采用VHDL硬件语言编写的。
上传时间： 2013-09-06
上传用户：zhouli
用vhdl编写的基于fpga的数字频率计程序算法
上传时间： 2013-09-07
上传用户：chfanjiang
LPC2106的双机SPI通讯,带PROTEUS仿真.收发程序均有.
上传时间： 2013-09-30
上传用户：tyler
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上传时间： 2014-12-23
上传用户：xinhaoshan2016
本文详细讨论了VHDL语句对PLD设计的影响和设计经验，经典文章，值得仔细阅读消化。,PLD Programming Using VHDL
标签： Programming Using VHDL PLD
上传时间： 2013-11-17
上传用户：teddysha
本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
标签： Verilog verilog System VHDL
上传时间： 2013-10-16
上传用户：牛布牛
多功能数字钟的VHDL设计
上传时间： 2013-10-29
上传用户：swz13842860183
51单片机综合学习系统-SPI总线
上传时间： 2014-01-27
上传用户：fudong911
SPI总线在51单片机系统中的实现
上传时间： 2013-11-15
上传用户：haoxiyizhong
基于MSP430的模拟SPI串口通信的实现
上传时间： 2013-11-23
上传用户：wfymay
