vhdl滤波

《VHDL实用教程》完整版

VHDL入门者值得学习!

标签： VHDL 实用教程

上传时间： 2013-11-06

上传用户：zhangfx728
VHDl实用教程(潘_松_王国栋_编著)

VHDL教程

标签： VHDl 实用教程

上传时间： 2015-01-01

上传用户：weiwolkt
vhdl 与数字电路设计

VHDL程序讲解，配合实例，适合初学者，大学期间可用

标签： vhdl 数字电路设计

上传时间： 2013-12-30

上传用户：米米阳123
XAPP105 - CPLD VHDL介绍

This introduction covers the fundamentals of VHDL as applied to Complex ProgrammableLogic Devices (CPLDs). Specifically included are those design practices that translate soundlyto CPLDs, permitting designers to use the best features of this powerful language to extractoptimum performance for CPLD designs.

标签： XAPP CPLD VHDL 105

上传时间： 2013-11-21

上传用户：gtf1207
The VHDL Cookbook (VHDL编码书籍)

The VHDL Cookbook是是VHDL编码书籍。

标签： VHDL Cookbook The 编码

上传时间： 2013-11-19

上传用户：lixqiang
US Navy VHDL Modelling Guide

This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.

标签： Modelling Guide Navy VHDL

上传时间： 2013-11-20

上传用户：pzw421125
PLD Programming Using VHDL

本文详细讨论了VHDL语句对PLD设计的影响和设计经验，经典文章，值得仔细阅读消化。,PLD Programming Using VHDL

标签： Programming Using VHDL PLD

上传时间： 2013-10-14

上传用户：www240697738
VHDL,Verilog,System verilog比较

本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

标签： Verilog verilog System VHDL

上传时间： 2014-03-03

上传用户：zhtzht
基于CPLD的VHDL语言数字钟(含秒表)设计

利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。

标签： CPLD VHDL 语言数字

上传时间： 2013-10-24

上传用户：古谷仁美
扩频通信芯片STEL-2000A的FPGA实现

针对传统集成电路（ASIC）功能固定、升级困难等缺点，利用FPGA实现了扩频通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核实现NCO模块，在下变频模块调用了硬核乘法器并引入CIC滤波器进行低通滤波，给出了DQPSK解调的原理和实现方法，推导出一种简便的引入?仔/4固定相移的实现方法。采用模块化的设计方法使用VHDL语言编写出源程序，在Virtex-II Pro 开发板上成功实现了整个系统。测试结果表明该系统正确实现了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.

标签： STEL 2000 FPGA 扩频通信

上传时间： 2013-11-19

上传用户：neu_liyan