vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
上传时间： 2016-05-05
上传用户：gundamwzc
在FPGA的嵌入式picoblaze设计中使用到的汇编器，在DOS下就可方便使用，方法：首先进行DOS命令窗，进行工作目录，运行kcpsm3 <filename>.psm 编译通过将生成vhd文件
上传时间： 2016-06-27
上传用户：sammi
四位十进制频率计设计 包含测频控制器（TESTCTL），4位锁存器(REG4B)，十进制计数器（CNT10）的原程序(vhd)，波形文件(wmf ),包装后的元件(bsf)。顶层原理图文件（Block1.bdf）和波形。
上传时间： 2016-11-21
上传用户：lijianyu172
交通灯控制器编码，源描述的编译顺序tlc.vhd，est_vector.vhd
上传时间： 2014-01-07
上传用户：海陆空653
空调系统有限状态自动机编码，各个源描述的编译顺序conditioner.vhd，conditioner_stim.vhd
上传时间： 2013-12-09
上传用户：watch100
是codic算法实现atan的virilog程序，模块结构如下：Core Structure: sc_corproc.vhd->p2r_cordic.vhd->p2r_cordicpipe.vhd
上传时间： 2017-02-01
上传用户：waizhang
The Synthetic PIC Verion 1.1 This a vhdL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the license agreement is stated in the main vhdL file, PICCPU.vhd and common questions are answered in the file SYNTHPIC.TXT Files: README.TXT This file.. SYNTHPIC.TXT Questions and Answers PICCPU.vhd Main processor vhdL file PICALU.vhd ALU for the PICCPU PICREGS.vhd Data memory PICROM.vhd Program memory (created by HEX2vhdL utility) PICTEST.vhd Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it. TEST2.ASM Another test program.. TEST3.ASM Yet another.. TEST4.ASM Yet another.. TEST5.ASM Yet another.. TEST6.ASM Yet another.. HEX2vhdL.CPP Utility for converting
标签： synthesizable microcontro Synthetic PIC
上传时间： 2013-12-22
上传用户：妄想演绎师
Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the sub-circuits can be used as smaller benchmarks.
标签： Stereo-Vision description Darabiha contains
上传时间： 2017-03-19
上传用户：comua
Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code.
标签： Transmitter controller Receiver Working
上传时间： 2013-12-27
上传用户：541657925
此文件为EDA的8位分频器，但可以用于不同位分频器，如：1位到10位等，用Quartus软件来，以文件vhd格式编译即可
上传时间： 2013-12-25
上传用户：003030
