verilog-A

VERILOG HDL 实际工控项目源码

VERILOG HDL 实际工控项目源码\r\n开发工具 altera quartus2

标签： VERILOG HDL 工控项目

上传时间： 2013-09-05

上传用户：youmo81
Cadence Verilog Language and Simulation

Cadence Verilog Language and Simulation

标签： Simulation Language Cadence Verilog

上传时间： 2013-09-06

上传用户：yl1140vista
gerber-to-protel is a pdf file

gerber-to-protel is a pdf file ,which is used for convert bmp to pcb.

标签： gerber-to-protel file is

上传时间： 2013-09-18

上传用户：liuxinyu2016
protel_lib-PIC16 is a protel lib file.

protel_lib-PIC16 is a protel lib file.

标签： protel_lib-PIC protel file lib

上传时间： 2013-09-18

上传用户：hn891122
Many CAD users dismiss schematic capture as a necessary evil in the process of creating

Many CAD users dismiss schematic capture as a necessary evil in the process of creating\r\nPCB layout but we have always disputed this point of view. With PCB layout now offering\r\nautomation of both component placement and track routing, getting the des

标签： schematic necessary creating dismiss

上传时间： 2013-09-25

上传用户：baiom
State Machine Coding Styles for Synthesis

本文论述了状态机的verilog编码风格,以及不同编码风格的优缺点，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.

标签： Synthesis Machine Coding Styles

上传时间： 2013-10-15

上传用户：dancnc
VHDL,Verilog,System verilog比较

本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

标签： Verilog verilog System VHDL

上传时间： 2013-10-16

上传用户：牛布牛
Verilog编码中的非阻塞性赋值

One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions

标签： Verilog 编码非阻塞性赋值

上传时间： 2013-10-17

上传用户：tb_6877751
常用D/A转换器和A/D转换器介绍

　　常用D/A转换器和A/D转换器介绍　　下面我们介绍一下其它常用D/A转换器和 A/D 转换器，便于同学们设计时使用。　　1. DAC0808 　　图 1 所示为权电流型 D/A 转换器 DAC0808 的电路结构框图。用 DAC0808 这类器件构成的 D/A转换器，需要外接运算放大器和产生基准电流用的电阻。DAC0808 构成的典型应用电路如图2 所示。

标签： 转换器

上传时间： 2014-12-23

上传用户：zhenyushaw
数电Verilog相关课件

数电Verilog相关课件

标签： Verilog 数电

上传时间： 2013-10-23

上传用户：wangzeng