This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 and PORT3.1 This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate simulation of all on-chip peripherals of the ADuC7000 device series. You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing constraints you configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.
标签： the Analyzer Compiler project
上传时间： 2013-12-19
上传用户：Yukiseop
ZigBee™ 是专为低速率传感器和控制网络设计的无线网络协议。有许多应用可从ZigBee 协议受益，其中可能的一些应用有：建筑自动化网络、住宅安防系统、工业控制网络、远程抄表以及PC 外设。此程序包提供的是Zigbee协义栈函数库源代码，它实现了一个与物理层 无关的应用程序接口。 因此，无需做重大修改就可以轻松地在射频（Radio Frequency，RF）收发器之间移植应用程序。
上传时间： 2014-01-16
上传用户：Pzj
Random Number Generators（随机数生成）包括gaussian random number generator、uniform random number generator、low-frequency hold generator、1/f noise generator等5种随机信号生成的c源代码
标签： generator random number Generators
上传时间： 2014-12-07
上传用户：edisonfather
频率调制，It is a diffrent matlab code for frequency modulation.
上传时间： 2015-05-30
上传用户：wanqunsheng
These instructions assume that the 1.4 versions of the java and appletviewer commands are in your path. If they aren t, then you should either specify the complete path to the commands or update your PATH environment variable as described in the installation instructions for the Java 2 SDK.
标签： instructions appletviewer the commands
上传时间： 2015-06-01
上传用户：3到15
Routine mampres: To obtain amplitude response from h(exp(jw)). input parameters: h :n dimensioned complex array. the frequency response is stored in h(0) to h(n-1). n :the dimension of h and amp. fs :sampling frequency (Hz). iamp:If iamp=0: The Amplitude Res. amp(k)=abs(h(k)) If iamp=1: The Amplitude Res. amp(k)=20.*alog10(abs(h(k))). output parameters: amp :n dimensioned real array. the amplitude-frequency response is stored in amp(0) to amp(n-1). Note: this program will generate a data file "filename.dat" . in chapter 2
标签： dimensione parameters amplitude response
上传时间： 2013-12-19
上传用户：xfbs821
Rotating shafts experience a an elliptical motion called whirl. It is important to decompose this motion into a forward and backward whil orbits. The current function makes use of two sensors to generate a bi-directional spectrogram. The method can be extended to any time-frequency distribution ％ ％ compute the forward/backward Campbell/specgtrogram ％ ％ INPUT: ％ y (n x 2) each column is measured from a different sensor ％ /////// ％ __ ％ |s1| y(:,1) ％ |__| ％ __ ％ / \ ________|/ ％ | | | s2 |/ y(:,2) ％ \____/ --------|/ ％ ％ Fs Sampling frequnecy ％ ％ OUTPUT: ％ B spectrogram/Campbel diagram ％ x x-axis coordinate vector (time or Speed) ％ y y-axis coordinate vector (frequency [Hz])
标签： experience elliptical decompose important
上传时间： 2015-06-23
上传用户：372825274
his project was built and tested with WinAVR-20060125. Make sure the MCU target define in the Makefiles corresponds to the AVR you are using!! To build the code, just install WinAVR and run "make" from the console in echomaster and echoslave subdirs. "make program" will program the device if you have a AVRISP attached. Remember to set the AVR device to at least 8MHz. The AVR may use the programmable clock from MC1319x, just remember to check if the MC1319x and SPI communication is working FIRST! Otherwise you wont get any clock signal to the AVR and then you can t program it or reset the fuses! The MC1319x has default clock output of 32kHz so you will have to set your programmer to a very low frequency (<=32kHz/4) to be able to program it while it is running on that!
标签： the 20060125 project WinAVR
上传时间： 2014-10-10
上传用户：yan2267246
关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
标签： investigates implementing pipelines circuits
上传时间： 2015-07-26
上传用户：CHINA526
describes the most common terms used in radarsystems, such as range, range resolution, Doppler frequency, and coherency. The second part of this chapter develops the radar range equation in many of its forms. This presentation includes the low PRF, high PRF,search, bistatic radar, and radar equation with jamming.
标签： range radarsystems resolution describes
上传时间： 2015-08-05
上传用户：宋桃子
