This article descrice how to use unnecessary I／O in the 51MCU to test the temperature, circuit is simple.
标签： temperature unnecessary the descrice
上传时间： 2016-06-11
上传用户：13517191407
Video cable driver amplifi er output stages traditionallyrequire a supply voltage of at least 6V in order to providethe required output swing. This requirement is usuallymet with 5V supplies by adding a boost regulator or asmall local negative rail, say via the popular LT®1983-3.Such additional circuitry is unnecessary in typical 1VP-Pvideo connections, such as HD component video, if thecable driver amplifi ers simply offer near rail-to-rail outputcapability when powered from 5V.
上传时间： 2013-11-16
上传用户：yanyangtian
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
In today’s IT environment, Java is a leading technology in the world of enterprise development. As management demands more from technology, complexity in infrastructure seems to grow exponentially, leaving many unable to keep up with the demands of such a fast-paced world. These complexities can be seen in the over-evolving Java 2 Enterprise Edition (J2EE) specifications. This unnecessary complexity drove us to discover ways of simplifying development.
标签： environment development enterprise technology
上传时间： 2013-12-24
上传用户：Zxcvbnm
ResOrg 图形化管理Vc项目的资源ID的工具的源代码。 ResOrg - Manage and Renumber Resource Symbol IDs Introduction The Resource ID Organiser (ResOrg for short) is an Add-in for Visual C++ designed to help overcome one of the most annoying (and unnecessary) chores of developing/maintaining Windows applications - maintaining resource symbol ID values.
标签： ResOrg Introduction Renumber Resource
上传时间： 2013-12-25
上传用户：dsgkjgkjg
Device-to-device(D2D) communications are now considered as an integral part of future 5G networks which will enable direct communication between user equipment (UE) without unnecessary routing via the network infrastructure. This architecture will result in higher throughputs than conventional cellular networks, but with the increased potential for co-channel interference induced by randomly located cellular and D2D UEs.
标签： Device-to-Device Communications Analysis of
上传时间： 2020-05-26
上传用户：shancjb
