Xilinx ultraScale™ 架构针对要求最严苛的应用，提供了前所未有的ASIC级的系统级集成和容量。 ultraScale架构是业界首次在All Programmable架构中应用最先进的ASIC架构优化。该架构能从20nm平面FET结构扩展至16nm鳍式FET晶体管技术甚至更高的技术，同 时还能从单芯片扩展到3D IC。借助Xilinx Vivado®设计套件的分析型协同优化，ultraScale架构可以提供海量数据的路由功能，同时还能智能地解决先进工艺节点上的头号系统性能瓶颈。 这种协同设计可以在不降低性能的前提下达到实现超过90%的利用率。 ultraScale架构的突破包括： • 几乎可以在晶片的任何位置战略性地布置类似于ASIC的系统时钟，从而将时钟歪斜降低达50% • 系统架构中有大量并行总线，无需再使用会造成时延的流水线，从而可提高系统速度和容量 • 甚至在要求资源利用率达到90%及以上的系统中，也能消除潜在的时序收敛问题和互连瓶颈 • 可凭借3D IC集成能力构建更大型器件，并在工艺技术方面领先当前行业标准整整一代 • 能在更低的系统功耗预算范围内显著提高系统性能，包括多Gb串行收发器、I/O以及存储器带宽 • 显著增强DSP与包处理性能 赛灵思ultraScale架构为超大容量解决方案设计人员开启了一个全新的领域。
标签： ultraScale Xilinx 架构
上传时间： 2013-11-17
上传用户：皇族传媒
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx ultraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® ultraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The ultraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the ultraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the ultraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx ultraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： ultraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
Xilinx ultraScale™ 架构针对要求最严苛的应用，提供了前所未有的ASIC级的系统级集成和容量。 ultraScale架构是业界首次在All Programmable架构中应用最先进的ASIC架构优化。该架构能从20nm平面FET结构扩展至16nm鳍式FET晶体管技术甚至更高的技术，同 时还能从单芯片扩展到3D IC。借助Xilinx Vivado®设计套件的分析型协同优化，ultraScale架构可以提供海量数据的路由功能，同时还能智能地解决先进工艺节点上的头号系统性能瓶颈。 这种协同设计可以在不降低性能的前提下达到实现超过90%的利用率。 ultraScale架构的突破包括： • 几乎可以在晶片的任何位置战略性地布置类似于ASIC的系统时钟，从而将时钟歪斜降低达50% • 系统架构中有大量并行总线，无需再使用会造成时延的流水线，从而可提高系统速度和容量 • 甚至在要求资源利用率达到90%及以上的系统中，也能消除潜在的时序收敛问题和互连瓶颈 • 可凭借3D IC集成能力构建更大型器件，并在工艺技术方面领先当前行业标准整整一代 • 能在更低的系统功耗预算范围内显著提高系统性能，包括多Gb串行收发器、I/O以及存储器带宽 • 显著增强DSP与包处理性能 赛灵思ultraScale架构为超大容量解决方案设计人员开启了一个全新的领域。
标签： ultraScale Xilinx 架构
上传时间： 2013-12-23
上传用户：小儒尼尼奥
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx ultraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® ultraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The ultraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the ultraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the ultraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx ultraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： ultraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
资料共9.77G，Zynq ultraScale+ MPSoC XCZU4EV平台，包括FPGA、SDK源码，例程源码，各种图像处理，人工智能算法，原理图，PCB，适合做项目移植、项目开发
上传时间： 2021-12-20
上传用户：
这是开发板资料，不是开发板，做硬件的可以参考里面的原理图和PCB，做软件的可以移植里面的工程
上传时间： 2022-03-26
上传用户：
8层全志A80BOX高清机顶盒AXT530124+EMMC-BGA169+AXP806原理图+PCB 8层飞思卡尔I.MX6x智能家居控制主板MAX8903C+WM8962+MT41K128M16JT 6层瑞芯微RK3288平板方案DSN+BRD 6层安霸A7LA30方案行车记录仪原理图和PCB文档 6层Rockchip_Wireless_HDMI_presentation的pcb+原理图下载 6层HI3531海思最新最全的硬件设计资料整合包含芯片手册，SCH和PCB 4层使用AM8252B做的带WiFi-HDMI功能的手机互联原理图和PCB 4层海思HI3535网络硬盘录像机PBGA563+QFN64+BGA96+原理图+PCB文件 4层MT7620A智能路由器（小米同款）原理图和PCB文件分享下载 2层STM32F107智能家居主板IR0038+SPX1117M3-3.3+CH340G+MOC3063原理图+PCB文件 2层LCD12864万年历(带原理图和PCB) 2层ESP8266系统板+CH340G+LM1117-V33+原理图+PCB文件分享下载 16层官方Xilinx Kintex ultraScale FPGA KCU105+4片DDR4分享下载 14层美高森美SmartFusion2 SOC FPGA开发板FT4232H+TPS51200+USB3340+原理图+PCB 14层高速板sch和brd文件下载 12层altera的5片DDR2组成72数据位宽 10层英特尔x86atom电脑主板BAYTRAIL+ISL95837HRZ-T+RTL8111GS原理图与PCB文件
标签： 实用电工
上传时间： 2013-04-15
上传用户：eeworm
