top-down

自顶向下（top-down）的分析算法通过在最左推导中描述出各个步骤来分析记号串输入。将大型的数字电路设计分割成大小不一的小模块来实现特定的功能，最后通过由顶层模块调用子模块来实现整体功能，这就是top-down的设计思想。

Hello User This is nothing, but a simple program which if kept in start of windows will shut down

Hello User This is nothing, but a simple program which if kept in start of windows will shut down the system by itself within five minutes of starting. It takes the time from the system & starts its timer to shut down after 5 minutes (not considering seconds). U can use shutdown.exe,once started there is only one exit that u know only. EXIT : DOUBLECLICK TIME TO ENABLE EXIT

标签： nothing program windows simple

上传时间： 2016-12-26

上传用户：lx9076
Hello User This is nothing, but a simple program which if kept in start of windows will shut down

Hello User This is nothing, but a simple program which if kept in start of windows will shut down the system by itself within five minutes of starting. It takes the time from the system & starts its timer to shut down after 5 minutes (not considering seconds). U can use shutdown.exe,once started there is only one exit that u know only. EXIT : DOUBLECLICK TIME TO ENABLE EXIT

标签： nothing program windows simple

上传时间： 2016-12-26

上传用户：yxgi5
Hello User This is nothing, but a simple program which if kept in start of windows will shut down

Hello User This is nothing, but a simple program which if kept in start of windows will shut down the system by itself within five minutes of starting. It takes the time from the system & starts its timer to shut down after 5 minutes (not considering seconds). U can use shutdown.exe,once started there is only one exit that u know only. EXIT : DOUBLECLICK TIME TO ENABLE EXIT

标签： nothing program windows simple

上传时间： 2014-03-06

上传用户：ruan2570406
FPGA程序的top.v文件

FPGA程序的top.v文件，主要实现DDS信号发生器功能，通过定时器，可简单实现输出幅值无极跳变

标签： FPGA top 程序

上传时间： 2013-11-26

上传用户：曹云鹏
本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v)

本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。

标签： EEPROM eeprom_wr verilog eeprom

上传时间： 2017-01-22

上传用户：lanjisu111
driver studio的key生成工具软件,有需要的就down.

driver studio的key生成工具软件,有需要的就down.

标签： driver studio down key

上传时间： 2013-12-26

上传用户：libinxny
土家人TOP.一个不错的FLASH网叶TOP,我感觉不错,不知大家意下如何

土家人TOP.一个不错的FLASH网叶TOP,我感觉不错,不知大家意下如何

标签： TOP FLASH 家

上传时间： 2013-12-30

上传用户：rocwangdp
都是PMSM电机方面的好文章,从学校的数据库里DOWN的

都是PMSM电机方面的好文章,从学校的数据库里DOWN的

标签： PMSM DOWN 电机方面

上传时间： 2014-01-22

上传用户：invtnewer
3D FDTD 计算程序 ToyFDTD1 is a stripped-down, minimalist, 3-dimensional FDTD code that is published un

3D FDTD 计算程序 ToyFDTD1 is a stripped-down, minimalist, 3-dimensional FDTD code that is published under the GNU General Public License. It is the first in the ToyFDTD series of codes, and it illustrates in heavily commented C and Fortran the basic tasks in implementing a simple 3D FDTD simulation.

标签： FDTD stripped-down dimensional minimalist

上传时间： 2013-12-25

上传用户：fhzm5658
自己实现的一个linux 下的top命令。

自己实现的一个linux 下的top命令。

标签： linux top 命令

上传时间： 2014-01-02

上传用户：LouieWu