One-channel queuing system simulator (M/M/1) * Arrival and service times are random and distributed exponetially. * * The simulator is time-slice-driven, i.e. the system model is being * run at discrete time points, with constant increments deltaT. * At each such time moment, program checks if a new item arrival or * release has occurred during previus deltaT.
标签： One-channel distributed and simulator
上传时间： 2014-01-15
上传用户：kr770906
verilog hdl编写,六段流水线CPU.程序完整，功能强惊。分为多模块编写
上传时间： 2013-12-10
上传用户：
数字边沿鉴相器 verilog源程序
上传时间： 2014-12-07
上传用户：爺的气质
Verilog and VHDL状态机设计，英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.
上传时间： 2013-12-19
上传用户：change0329
Verilog 程序例子 王金明：《Verilog HDL程序设计教程》程序例子，带说明。
上传时间： 2014-01-08
上传用户：star_in_rain
用verilog设计密勒解码器 一、题目： 设计一个密勒解码器电路 二、输入信号： 1． DIN：输入数据 2． CLK：频率为2MHz的方波，占空比为50％ 3． RESET：复位信号，低有效 三、输入信号说明： 输入数据为串行改进密勒码，每个码元持续时间为8μs，即16个CLK时钟；数据流是由A、B、C三种信号组成； A：前8个时钟保持“1”，接着5个时钟变为“0”，最后3个时钟为“1”。 B：在整个码元持续时间内都没有出现“0”，即连续16个时钟保持“1”。 C：前5个时钟保持“0”，后面11个时钟保持“1”。 改进密勒码编码规则如下： 如果码元为逻辑“1”，用A信号表示。 如果码元为逻辑“0”，用B信号表示，但以下两种特例除外：如果出现两个以上连“0”，则从第二个“0”起用C信号表示；如果在“通信起始位”之后第一位就是“0”，则用C信号表示，以下类推； “通信起始位”，用C信号表示； “通信结束位”，用“0”及紧随其后的B信号表示。 “无数据”，用连续的B信号表示。
上传时间： 2013-12-02
上传用户：wang0123456789
In this paper, we describe the development of a mobile butterfly-watching learning (BWL) system to realize outdoor independent learning for mobile learners. The mobile butterfly-watching learning system was designed in a wireless mobile ad-hoc learning environment. This is first result to provide a cognitive tool with supporting the independent learning by applying PDA with wireless communication technology to extend learning outside of the classroom. Independent learning consists of self-selection, self-determination, self-modification, and self-checking.
标签： butterfly-watching development describe learning
上传时间： 2014-11-26
上传用户：waizhang
FHSS_DSSS_CDMA system simulation with MATLAB
标签： FHSS_DSSS_CDMA simulation system MATLAB
上传时间： 2013-12-18
上传用户：569342831
This is a boiler test system,has been use in factory
标签： factory boiler system This
上传时间： 2015-09-24
上传用户：许小华
This file is part of the RTX-51 Real-Time Operating System Source Package
标签： Operating Real-Time Package System
上传时间： 2014-01-03
上传用户：caozhizhi
