verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过
上传时间： 2015-08-13
上传用户：xinyuzhiqiwuwu
verilog实现电子时钟模块，输入60Hz时钟信号和复位，输出时分秒，共6位，每位7段输出用于驱动
上传时间： 2015-08-13
上传用户：王楚楚
verilog实现，UDP描述带有异步复位的正边沿触发D触发器，test测试通过
标签： verilog
上传时间： 2013-12-27
上传用户：yulg
verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送
标签： verilog
上传时间： 2015-08-13
上传用户：妄想演绎师
I2C总线verilog实现源码，可以完整实现I2C bus的基本功能
上传时间： 2015-08-13
上传用户：anng
usb1.1的对sd卡的读写的verilog代码,攻大家参考设计.
上传时间： 2015-08-14
上传用户：清风冷雨
J2ME中RMS（Record Manager System）的使用解析
标签： Manager Record System J2ME
上传时间： 2015-08-14
上传用户：sqq
This m file models an UWB system using BPSK. The receiver is a correlation receiver with a LPF integrator and comparators for threshhold selection.
标签： receiver correlation models system
上传时间： 2014-12-19
上传用户：ryb
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis to the public transportation systems engineering to design ,Java,software engineering
标签： transportation engineering documents including
上传时间： 2015-08-15
上传用户：lixinxiang
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis to the public transportation systems engineering to design ,Java,software
标签： transportation engineering documents including
上传时间： 2013-12-26
上传用户：Zxcvbnm
