这篇文章讨论了不同HDL代码的编写方式，对综合结果的影响。阅读本文对深入了解综合工具和提高HDL的编写水平有不少帮助，原文时针对Synopsys的综合软件论述的，但对所有综合软件，都有普遍的借鉴意义
标签： synthesis Coding Styles Guide
上传时间： 2014-12-23
上传用户：huql11633
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
标签： Creating Machines Mentor State
上传时间： 2013-10-08
上传用户：wangzhen1990
文章提出了一种精简指令集8 位单片机中, 算术逻辑单元的工作原理。在此基础上, 对比传统PIC 方案、以及在ALU 内部再次采用流水线作业的332 方案、44 方案, 并用Synopsys 综合工具实现了它们。综合及仿真结果表明, 根据该单片机系统要求, 44 方案速度最高, 比332 方案可提高43.9%, 而面积仅比最小的332 方案增加1.6%。在分析性能差异的根本原因之后, 阐明了该方案的优越性。关键词: 单片机, 精简指令集, 算术逻辑单元, 流水线 Abstract: Work principle for ALU in an 8_bit RISC Singlechip microcomputer is described. The traditional PIC scheme, 332 Pipeline scheme and 44 Pipeline scheme are compared on the base of the principle, which are implemented using Synopsys design tools. Results from synthesis and simulation shows that 44 scheme operates the fast, which is 43.9% faster and only 1.6% larger than 332 scheme. The essential reason why the performance is so different is analyzed.Then the advantage of 44 scheme is clarified.Key words: Singlechip, Microcomputer, RISC, ALU, Pipeline
上传时间： 2013-10-18
上传用户：xiaoyaa
FPGA synthesis with the Synplify_Pro Tool
标签： FPGA_synthesis_with_the_Synplify_ Pro_Tool
上传时间： 2013-10-28
上传用户：aa54
FPGA synthesis with the Synplify_Pro Tool
标签： FPGA_synthesis_with_the_Synplify_ Pro_Tool
上传时间： 2014-11-05
上传用户：huyanju
这篇文章讨论了不同HDL代码的编写方式，对综合结果的影响。阅读本文对深入了解综合工具和提高HDL的编写水平有不少帮助，原文时针对Synopsys的综合软件论述的，但对所有综合软件，都有普遍的借鉴意义
标签： synthesis Coding Styles Guide
上传时间： 2014-01-11
上传用户：亚亚娟娟123
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
标签： Creating Machines Mentor State
上传时间： 2013-11-02
上传用户：xauthu
本文利用Verilog HDL 语言自顶向下的设计方法设计多功能数字钟，突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点，并通过Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成综合、仿真。此程序通过下载到FPGA 芯片后，可应用于实际的数字钟显示中。 关键词：Verilog HDL；硬件描述语言；FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA
上传时间： 2013-11-10
上传用户：hz07104032
IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level synthesis.rar
上传时间： 2013-12-23
上传用户：erkuizhang
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
标签： system-on-chip integrated designed reusable
上传时间： 2013-12-20
上传用户：小眼睛LSL
