Solve the 8-puzzle problem using A * algorithme. Input: Program reads start state and goal state and heuristic (N or S) from EightPuzzle.INP file.0 representing blank. There are 2 Heuristic: 1. N: Number of misplaced tiles 2. S: Sum of Manhattan distance of current location and target location. Format: The first line write type of heuristic (N or S). Next is the status of departing and landing status. Between 2 states of 1 line blank. See examples EightPuzzle.INP
标签： state algorithme Program problem
上传时间： 2017-08-12
上传用户：jjj0202
The STi7105 uses state of the art process technology to provide an ultra low-cost, fully featured HD AVC decoder IC. It is a highly integrated system-on-chip suitable for STB markets across all networks (cable/satellite/DTT/x- DSL/IP) worldwide
标签： technology low-cost featured process
上传时间： 2013-12-22
上传用户：时代电子小智
本备忘录说明了OSPF协议版本2。OSPF是一种连接状态/link-state路由协议，被设计用于单一的自制系统/Autonomous System中。每个OSPF路由器都维持着同样的数据库以描述AS的拓扑结构，并以此数据库来创建最短路径树并计算路由表。
标签： OSPF link-state 协议 版本
上传时间： 2017-09-19
上传用户：youlongjian0
Transition-Time Optimization for Switched-Mode Dynamical Systems
标签： Transition-Time Switched-Mode Optimization Dynamical
上传时间： 2017-09-28
上传用户：xinyuzhiqiwuwu
随着社会的发展以及能源、环保等问题的日益突出，纯电动汽车以其零排放，噪声低等优点越来越受到世界各国的重视，被称作绿色环保车。作为发展电动车的关键技术之一的电池管理系统(BMS)，是电动车产业化的关键。本课题配合“基于开关磁阻电机的电动汽车的研制”，研制适用于纯电动汽车的电池管理系统。 电池管理系统直接检测及管理电动汽车的储能电池运行的全过程，包括电池基本信息测量、电量估计、单体电池间的均衡、电池故障诊断几个方面。 本论文主要工作是研制适用于纯电动汽车的蓄电池管理系统。研究铅酸蓄电池二阶模型的建立与剩余容量的卡尔曼滤波估算方法。分析铅酸蓄电池的基本工作原理和影响蓄电池组剩余容量SOC(state of charge)的主要因素。 介绍了基于DSP2407的蓄电池组控制器的硬件平台，完成DSP小系统、电池数据采集电路、信号调理电路、CAN总线相关电路等硬件电路设计、调试、完善。独立完成系统所有软件设计，包括：主程序设计，电池基本信息检测子程序设计，电池剩余电量卡尔曼滤波估算程序设计，电池状态检测子程序设计，CAN收发子程序设计，EEPROM读写子程序设计。 最后，在电动汽车上搭建实验平台，将铅酸蓄电池组与设计的软硬件系统联合进行调试、试验。测得了相关数据。试验结果表明，本文介绍的电池管理系统硬件电路可靠、经济、抗干扰能力强。可以实现：电池电压、电流、温度的模拟量采集；剩余电量的计算和电池状态的判断；实时显示，故障时报警等BMS相关功能。
上传时间： 2013-06-11
上传用户：hustfanenze
并行总线PATA从设计至今已快20年历史，如今它的缺陷已经严重阻碍了系统性能的进一步提高，已被串行ATA(Serial ATA)即SATA总线所取代。SATA作为新一代磁盘接口总线，采用点对点方式进行数据传输，内置数据/命令校验单元，支持热插拔，具有150MB/s(SATA1.0)或300MB/s(SATA2.0)的传输速度。目前SATA已在存储领域广泛应用，但国内尚无独立研发的面向FPGA的SATAIP CORE，在这样的条件下设计面向FPGA应用的SATA IP CORE具有重要的意义。 本论文对协议进行了详细的分析，建立了SATA IP CORE的层次结构，将设备端SATA IP CORE划分成应用层、传输层、链路层和物理层；介绍了实现该IPCORE所选择的开发工具、开发语言和所选用的芯片；在此基础上着重阐述协议IP CORE的设计，并对各个部分的设计予以分别阐述，并编码实现；最后进行综合和测试。 采用FPGA集成硬核RocketIo MGT(RocketIo Multi-Gigabit Transceiver)实现了1.5Gbps的串行传输链路；设计满足协议需求、适合FPGA设计的并行结构，实现了多状态机的协同工作：在高速设计中，使用了流水线方法进行并行设计，以提高速度，考虑到系统不同部分复杂度的不同，设计采用部分流水线结构；采用在线逻辑分析仪Chipscope pro与SATA总线分析仪进行片上调试与测试，使得调试工作方便快捷、测试数据准确；严格按照SATA1.0a协议实现了SATA设备端IP CORE的设计。 最终测试数据表明，本论文设计的基于FPGA的SATA IP CORE满足协议需求。设计中的SATA IP CORE具有使用方便、集成度高、成本低等优点，在固态电子硬盘SSD(Solid-State Disk)开发中应用本设计，将使开发变得方便快捷，更能够适应市场需求。
上传时间： 2013-06-21
上传用户：xzt
英文描述： OCTAL BUFFER/LINE DRIVERS WITH 3-STATE OUTPUT(NONINVERTED) 中文描述： 八路缓冲器/线路驱动器具有三态输出（NONINVERTED）
上传时间： 2013-04-24
上传用户：chengli008
Recently a new technology for high voltage Power MOSFETshas been introduced – the CoolMOS™ . Based on thenew device concept of charge compensation the RDS(on) areaproduct for e.g. 600V transistors has been reduced by afactor of 5. The devices show no bipolar current contributionlike the well known tail current observed during the turn-offphase of IGBTs. CoolMOS™ virtually combines the lowswitching losses of a MOSFET with the on-state losses of anIGBT.
标签： COOLMOS
上传时间： 2013-11-14
上传用户：zhyiroy
Most circuit designers are familiar with diode dynamiccharacteristics such as charge storage, voltage dependentcapacitance and reverse recovery time. Less commonlyacknowledged and manufacturer specifi ed is diode forwardturn-on time. This parameter describes the timerequired for a diode to turn on and clamp at its forwardvoltage drop. Historically, this extremely short time, unitsof nanoseconds, has been so small that user and vendoralike have essentially ignored it. It is rarely discussed andalmost never specifi ed. Recently, switching regulator clockrate and transition time have become faster, making diodeturn-on time a critical issue. Increased clock rates aremandated to achieve smaller magnetics size; decreasedtransition times somewhat aid overall effi ciency but areprincipally needed to minimize IC heat rise. At clock speedsbeyond about 1MHz, transition time losses are the primarysource of die heating.
上传时间： 2013-10-10
上传用户：谁偷了我的麦兜
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
上传时间： 2013-11-12
上传用户：pans0ul
