A Java virtual machine instruction consists of an opcode specifying the operation to be performed, followed by zero or more operands embodying values to be operated upon. This chapter gives details about the format of each Java virtual machine instruction and the operation it performs.
标签： instruction specifying operation performed
上传时间： 2014-01-11
上传用户：yiwen213
A Java virtual machine instruction consists of an opcode specifying the operation to be performed, followed by zero or more operands embodying values to be operated upon. This chapter gives details about the format of each Java virtual machine instruction and the operation it performs.
标签： instruction specifying operation performed
上传时间： 2015-05-02
上传用户：daoxiang126
A Java virtual machine instruction consists of an opcode specifying the operation to be performed, followed by zero or more operands embodying values to be operated upon. This chapter gives details about the format of each Java virtual machine instruction and the operation it performs.
标签： instruction specifying operation performed
上传时间： 2015-05-02
上传用户：shawvi
A Java virtual machine instruction consists of an opcode specifying the operation to be performed, followed by zero or more operands embodying values to be operated upon. This chapter gives details about the format of each Java virtual machine instruction and the operation it performs.
标签： instruction specifying operation performed
上传时间： 2013-12-12
上传用户：朗朗乾坤
There are three ways of specifying an immediate dump Immediate dumps can be specified using the ALTER SESSION command ALTER SESSION SET EVENTS immediate trace name dump level level Immediate dumps can be specified in ORADEBUG ORADEBUG DUMP dump level
标签： specifying Immediate immediate specified
上传时间： 2014-01-17
上传用户：mpquest
Abstract: This application note describes how sampling clock jitter (time interval error or "TIE jitter") affectsthe performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importanceof separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2xpassband frequency) jitter tolerance in these devices. The article also provides an application example ofa simple highly jittered cycle-skipped sampling clock and describes a method for generating a properbroadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance tocompetitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sampleclock implementations.
上传时间： 2013-10-25
上传用户：banyou
Abstract: Most magnetic read head data sheets do not fully specify the frequency-dependent components andare often vague when specifying other key parameters. In some cases, the specifications of two very similarheads from two different manufacturers might be quite different in terms of parameters specified and omitted.The limitations in the data sheets make designing an optimum card reading system unnecessarily difficult andtime consuming. This document outlines a strategy to overcome the above shortcomings and offers guidelinesto overcome the noise issues.
上传时间： 2013-11-13
上传用户：dysyase
specifying the right reference and applying it correctly isa more difficult task than one might first surmise, consideringthat references are only 2- or 3-terminal devices.Although the word “accuracy” is most often spoken inreference to references, it is dangerous to use this wordtoo freely because it can mean different things to differentpeople. Even more perplexing is the fact that a referenceclassified as a dog in one application is a panacea inanother. This application note will familiarize the readerwith the various aspects of reference “accuracy” andpresent some tips on extracting maximum performancefrom any reference.
标签： 电压基准
上传时间： 2013-10-15
上传用户：liuwei6419
完整性高的FPGA-PCB系统化协同设计工具 Cadence OrCAD and Allegro FPGA System Planner便可满足较复杂的设计及在设计初级产生最佳的I/O引脚规划，并可透过FSP做系统化的设计规划，同时整合logic、schematic、PCB同步规划单个或多个FPGA pin的最佳化及layout placement，借由整合式的界面以减少重复在design及PCB Layout的测试及修正的过程及沟通时间，甚至透过最佳化的pin mapping、placement后可节省更多的走线空间或叠构。 specifying Design Intent 在FSP整合工具内可直接由零件库选取要摆放的零件，而这些零件可直接使用PCB内的包装，预先让我们同步规划FPGA设计及在PCB的placement。
标签： Allegro Planner System FPGA
上传时间： 2013-11-06
上传用户：wwwe
完整性高的FPGA-PCB系统化协同设计工具 Cadence OrCAD and Allegro FPGA System Planner便可满足较复杂的设计及在设计初级产生最佳的I/O引脚规划，并可透过FSP做系统化的设计规划，同时整合logic、schematic、PCB同步规划单个或多个FPGA pin的最佳化及layout placement，借由整合式的界面以减少重复在design及PCB Layout的测试及修正的过程及沟通时间，甚至透过最佳化的pin mapping、placement后可节省更多的走线空间或叠构。 specifying Design Intent 在FSP整合工具内可直接由零件库选取要摆放的零件，而这些零件可直接使用PCB内的包装，预先让我们同步规划FPGA设计及在PCB的placement。
标签： Allegro Planner System FPGA
上传时间： 2013-10-19
上传用户：shaojie2080
