Short description: GUI Ant-Miner is a tool for extracting classification rules from data. It is an updated version of a data mining algorithm called Ant-Miner (Ant Colony-based Data Miner), which was proposed in 2002 by Parpinelli, Lopes and Freitas. GUI Ant-Miner differs from the original algorithm as follows: It has a friendly graphical user interface, makes possible the use of ant populations within the Ant Colony Optimization (ACO) concept, data input file is standardized with the well-known Weka system, and runs on virtually any operating system since it is written in Java.
标签： classification description extracting Ant-Miner
上传时间： 2013-12-18
上传用户：gonuiln
BGP-Broder Gateway Protocol which is a set rules govern by some functions which interconnects 2 autonomous systems.
标签： which interconnects BGP-Broder functions
上传时间： 2017-07-29
上传用户：gxf2016
The goal of this thesis is the development of traffic engineering rules for cellular packet radio networks based on GPRS and EDGE. They are based on traffic models for typical mobile applications. Load generators, representing these traffic models, are developed and integrated into a simulation environment with the prototypical implementation of the EGPRS protocols and models for the radio channel, which were also developed in the framework of this thesis. With this simulation tool a comprehensive performance evaluation is carried out that leads to the traffic engineering rules.
标签： development engineering cellular traffic
上传时间： 2014-01-11
上传用户：Miyuki
Logic2007中文教程 PADS Logic功能，特点及使用教程 本教程描述了PADS Logic 的各种功能和特点、以及使用方法。这些功 能包括： 如何在PADS Logic 中使用工作区(Working Area)。 如何在PADS Logic 的元件库中定义目标库(Library)。 如何从库中搜索有关的元件(Part)。 如何添加连线(Connection)、总线(Bus)、使用页间连接符号 移动(Move)、拷贝(Copy)、删除(Delete)和编辑(Edit)等操作方式(Mode)。 在设计数据编辑时使用查询/修改(Query/Modify)命令。 如何定义设计规则(Design rules)。 如何建立网表(Netlist)和SPICE 格式网络表以及材料清单(BOM)报
上传时间： 2013-04-24
上传用户：zhaoq123
在AD PCB 环境下，Design>rules>Plane> Polygon Connect style ,点中Polygon Connect style，右键点击new rule ---新建一个规则点击新建的规则既选中该规则，在name 框中改变里面的内容即可修改该规则的名称，默认是PolygonConnect_1 ，现我们修改为GND-Via.
上传时间： 2013-10-29
上传用户：yunfan1978
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上传时间： 2013-10-22
上传用户：ztj182002
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上传时间： 2013-11-21
上传用户：不懂夜的黑
在AD PCB 环境下，Design>rules>Plane> Polygon Connect style ,点中Polygon Connect style，右键点击new rule ---新建一个规则点击新建的规则既选中该规则，在name 框中改变里面的内容即可修改该规则的名称，默认是PolygonConnect_1 ，现我们修改为GND-Via.
上传时间： 2014-08-06
上传用户：leixinzhuo
dasniff daSniff is an open source customizable sniffer for win32 systems. It helps you to log your LAN traffic by specifying packet rules as filters.
标签： customizable dasniff daSniff sniffer
上传时间： 2013-12-19
上传用户：invtnewer
Description: C4.5Rule-PANE is a rule learning method which could generate accurate and comprehensible symbolic rules, through regarding a neural network ensemble as a pre-process of a rule inducer. Reference: Z.-H. Zhou and Y. Jiang. Medical diagnosis with C4.5 rule preceded by artificial neural network ensemble. IEEE Transactions on Information Technology in Biomedicine, 2003, vol.7, no.1, pp.37-42. 使用神经网络集成方法诊断糖尿病,肝炎,乳腺癌症的案例研究.
标签： comprehensibl Description Rule-PANE accurate
上传时间： 2013-11-30
上传用户：wcl168881111111
