SMC takes a state machine stored in a .sm file and generates a State pattern in twelve programming languages. Includes: default transitions, transition args, transition guards, push/pop transitions and Entry/Exit actions. See User Manual for more info.
标签： programming generates machine pattern
上传时间： 2013-12-25
上传用户：gaome
this program solves the steady-state navier-stokes eqn in 2d for the flow in a driven cavity problem. the function solved for is the streamfunction. the velocity may be obtained by differentiating the streamfunction.
标签： navier-stokes steady-state the program
上传时间： 2014-01-06
上传用户：himbly
advantage of Channel state information at Txer
标签： information advantage Channel state
上传时间： 2017-05-22
上传用户：66666
state flow program in Matlab simulink.
标签： simulink program Matlab state
上传时间： 2017-05-23
上传用户：hn891122
kalman filter with state constraints lecture and example
标签： constraints example lecture kalman
上传时间： 2013-12-02
上传用户：gxmm
GPIO (General Purpose Input and Output ports) with microprocessor programmable tri-state bus interface
标签： microprocessor programmable tri-state General
上传时间： 2017-06-13
上传用户：hxy200501
用状态机实现密码锁State machine used to achieve code lock
标签： machine achieve State code
上传时间： 2017-06-21
上传用户：a673761058
This volume presents the state of the art concerning quality and interestingness measures for data mining. The book summarizes recent developments and presents original research on this topic. The chapters include surveys, comparative studies of existing measures, proposals of new measures, simulations, and case studies. Both theoretical and applied chapters are included. Papers for this book were selected and reviewed for correctness and completeness by an international review committee.
标签： interestingness concerning the presents
上传时间： 2014-01-19
上传用户：ve3344
LMS: Least Mean Square the source code for state space environment.
标签： environment Square source Least
上传时间： 2013-12-25
上传用户：xzt
Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.
标签： synchronous Designing engineer digital
上传时间： 2014-01-17
上传用户：dreamboy36
