The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
标签： Transceiver Virtex Wizar GTP
上传时间： 2013-10-23
上传用户：leyesome
文中在pre-FFT定时同步算法的基础上提出一个新的定时同步算法及其改进算法，该算法利用规则集对相关函数和导函数优化的方法得以进一步减小估计方差，本文在给出其推导过程的基础上给出了仿真结果，并与相关算法进行比较，结果表明新算法的定时估计精度较高且具有一定的鲁棒性。
上传时间： 2013-10-29
上传用户：hebmuljb
Multioutput monolithic regulators are easy to use and fi tinto spaces where multichip solutions cannot. Nevertheless,the popularity of multioutput regulators is temperedby a lack of options for input voltages above 30V andsupport of high output currents. The LT3692A fi lls thisgap with a dual monolithic regulator that operates frominputs up to 36V. It also includes a number of channeloptimization features that allow the LT3692A’s per-channelperformance to rival that of multichip solutions.
上传时间： 2014-01-03
上传用户：Huge_Brother
The RT9005A/B is a dual-output Linear regulator for DDR-SDRAM VDDQ supply and termination voltage VTT supply.
上传时间： 2013-11-13
上传用户：lmq0059
The RT9018A/B is a high performance positive voltage regulator designed for use in applications requining very low Input voltage and very low dropout voltage at up to 3A(peak).
上传时间： 2013-10-10
上传用户：geshaowei
12864液晶时钟显示程序 LCD 地址变量 ;**************变量的定义***************** RS BIT P2.0 ;LCD数据/命令选择端(H/L) RW BIT P2.1 ;LCD读/写选择端(H/L) EP BIT P2.2 ;LCD使能控制 PSB EQU P2.3 RST EQU P2.5 PRE BIT P1.4 ;调整键(K1) ADJ BIT P1.5 ;调整键(K2) COMDAT EQU P0 LED EQU P0.3 YEAR DATA 18H ;年,月,日变量 MONTH DATA 19H DATE DATA 1AH WEEK DATA 1BH HOUR DATA 1CH ;时,分,秒,百分之一秒变量 MIN DATA 1DH SEC DATA 1EH SEC100 DATA 1FH STATE DATA 23H LEAP BIT STATE.1 ;是否闰年标志1--闰年，0--平年 KEY_S DATA 24H ;当前扫描键值 KEY_V DATA 25H ;上次扫描键值 DIS_BUF_U0 DATA 26H ;LCD第一排显示缓冲区 DIS_BUF_U1 DATA 27H DIS_BUF_U2 DATA 28H DIS_BUF_U3 DATA 29H DIS_BUF_U4 DATA 2AH DIS_BUF_U5 DATA 2BH DIS_BUF_U6 DATA 2CH DIS_BUF_U7 DATA 2DH DIS_BUF_U8 DATA 2EH DIS_BUF_U9 DATA 2FH DIS_BUF_U10 DATA 30H DIS_BUF_U11 DATA 31H DIS_BUF_U12 DATA 32H DIS_BUF_U13 DATA 33H DIS_BUF_U14 DATA 34H DIS_BUF_U15 DATA 35H DIS_BUF_L0 DATA 36H ;LCD第三排显示缓冲区 DIS_BUF_L1 DATA 37H DIS_BUF_L2 DATA 38H DIS_BUF_L3 DATA 39H DIS_BUF_L4 DATA 3AH DIS_BUF_L5 DATA 3BH DIS_BUF_L6 DATA 3CH DIS_BUF_L7 DATA 3DH DIS_BUF_L8 DATA 3EH DIS_BUF_L9 DATA 3FH DIS_BUF_L10 DATA 40H DIS_BUF_L11 DATA 41H DIS_BUF_L12 DATA 42H DIS_BUF_L13 DATA 43H DIS_BUF_L14 DATA 44H DIS_BUF_L15 DATA 45H FLAG DATA 46H ;1-年，2-月，3-日，4-时，5-分，6-秒，7-退出调整。 DIS_H DATA 47H DIS_M DATA 48H DIS_S DATA 49H
上传时间： 2013-11-09
上传用户：xingisme
收文单位：左列各单位 发文字号： MT-8-2-0037
上传时间： 2013-10-28
上传用户：ming529
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
标签： Transceiver Virtex Wizar GTP
上传时间： 2013-10-20
上传用户：dave520l
这个软件需要你的本机操作的。其他机器是算不出来的！ 就是说 一台电脑只有一个注册码对应！ 这里有个办法： MULTISIM2001安装方法： 一：运行SETUP.EXE安装。在安装时，要重新启动计算机一次。 二：启动后在“开始>程序”中找到STARTUP项，运行后，继续进行安装，安装过程中，第一次要求输入“CODE"码时， 输入“PP-0411-48015-7464-32084"输入后，会提示"VALID SERIAL NUMBER FOR MULTISIM 2001 POWER-PRO." 按确定，又会出现一个“feature code”框，输入“FC-6424-04180-0044-13881”后， 在弹出的对话框中选择“取消”，一路确定即可完成安装。 三：1.运行VERILOG目录内的SETUP安装 2.运行FPGA目录内的SETUP安装 3.将CRACK目录内的LICMGR.DLL拷贝到WINDOWS系统的SYSTEM 目录内 4.并将VERILOG安装目录内的同名文件删除 5.将SILOS.LIC文件拷到VERILOG安装目录内覆盖原文件，并作如下编辑： 6.将“COMPUTER_NAME”替换为你的机器名 7.将“D:\MULTISIM\VERILOG\PATH_TO_SIMUCAD.EXE”替换为你的 实际安装路径。如此你便可以使用VERILOG了。 四：安装之后，运行MULTISIM2001,会要求输入“RELEASE CODE",不用着急， 记下“SERIAL NUMBER"和“SIGNATURE NUMBER", 使用CRACK目录内的注册器“MULTISIM KEYGEN.EXE" 将刚才记下的两个号码分别填入后， 即可得到"RELEASE CODE", 以后就可以正常使用了。 五：接下来运行 database update目录中的几个文件， 进行数据库合并即可。祝你成功！！ 六：启动MULTISIM2001时候的注册码 1： PP-0411-48015-7464-32084 2： 37506-86380 3:的三个空格 1975 2711 4842 里面包含了：Multisim2001汉化破解版、Multisim.V10.0.1.汉化破解版图解 解压密码：www.pp51.com
上传时间： 2013-11-16
上传用户：天空说我在
Semiconductor memory, card readers, microprocessors,disc drives, piezoelectric devices and digitally based systemsfurnish transient loads that a voltage regulator mustservice. Ideally, regulator output is invariant during a loadtransient. In practice, some variation is encountered andbecomes problematic if allowable operating voltage tolerancesare exceeded. This mandates testing the regulatorand its associated support components to verify desiredperformance under transient loading conditions. Variousmethods are employable to generate transient loads, allowingobservation of regulator response
上传时间： 2013-11-21
上传用户：semi1981
