ACPCI系列的产品就是专为工控机和台式机及其他电脑工程项目和测试调试设计的。和计算机的连接接口是通用的PCI接口，ACPCI是南京来可电子根据多年的CAN总线工程应用经验总结而成的，力求在CAN总线的兼容性、稳定性和标准性上做到最好，ACPCI的单通道发送速度最高大于5000帧/秒，单通道接收速度最高大于7000帧/秒。总线2500V DC-DC隔离，总线接口防雷击浪涌保护，配套有免费的测试软件Adawin CANTest，方便对卡和客户的CAN应用系统进行测试。
上传时间： 2013-11-08
上传用户：born2007
通过对刀片服务器基本概念、主要组成以及内部架构的分析和研究，针对刀片与主板之间的高速通信需求，采用PCI总线作为系统的数据通信协议，给出了PCI局部总线的详细分析和设计流程，以及系统所采用的"PCI＋FPGA＋FLASH"方案的具体实现方法和步骤，最后给出了实际的测试验证结果，相关结论，对设计PCI通信系统具有较强的借鉴意义。
上传时间： 2013-10-30
上传用户：liuxinyu2016
VxWorks是WindRiver（风河）公司开发的嵌入式实时操作系统（RTOS），由于它的高实时性，所以广泛地应用于军事、工业控制、通信等领域；分析了VxWorks下PCI总线多功能数据采集卡的实现方法；以ADLINK的PCI7396数据采集卡为例，介绍PCI总线设备的配置空间，包括它的结构及访问方法，重点介绍PCI总线设备在VxWorks下驱动程序的开发步骤及编程要点，并对开发过程中的关键部分给予代码说明；在某综合控制系统中，开发的驱动程序运行稳定、可靠。
上传时间： 2013-11-02
上传用户：masochism
利用PCI专用接口芯片PCI9052和DEI1016 429总线收发芯片设计了ARINC429接口卡，采用DSP作为主控CPU完成数据自动处理，用双口RAM完成DSP与PCI总线数据交换。实验表明：所设计的接口卡传输效率高，可靠性好，开发简单。
上传时间： 2014-12-30
上传用户：love1314
PCI总线是目前最为流行的一种局部性总线 通过对PCI总线一些典型功能的分析以及时序的阐述，利用VetilogHDL设计了一个将非PCI功能设备转接到PC1总线上的IP Core 同时，通过在ModeISim SE PLUS 6．0 上运行测试程序模块，得到了理想的仿真数据波形，从软件上证明了功能的实现。
上传时间： 2014-12-30
上传用户：himbly
The PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.
上传时间： 2013-11-01
上传用户：KSLYZ
作为一种独立于处理器的局部总线,PCI非常适用于网络适配器、硬盘驱动器、全动态视频卡、图形卡及各类高速外设。据称,目前有90%的Pentium处理器采用PCI做为系统总线。
上传时间： 2013-11-07
上传用户：liaocs77
PCI Express是由Intel，Dell，Compaq，IBM，Microsoft等PCI SIG联合成立的Arapahoe Work Group共同草拟并推举成取代PCI总线标准的下一代标准。PCI Express利用串行的连接特点能轻松将数据传输速度提到一个很高的频率，达到远远超出PCI总线的传输速率。一个PCI Express连接可以被配置成x1，x2，x4，x8，x12，x16和x32的数据带宽。x1的通道能实现单向312.5 MB／s（2.5 Gb／s）的传输速率。Xilinx公司的Virtex5系列FPGA芯片内嵌PCI-ExpressEndpoint Block硬核，为实现单片可配置PCI-Express总线解决方案提供了可能。 本文在研究PCI-Express接口协议和PCI-Express Endpoint Block硬核的基础上，使用Virtex5LXT50 FPGA芯片设计PCI Express接口硬件电路，实现PCI-Express数据传输
上传时间： 2013-12-27
上传用户：wtrl
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 图Figure 1. Local Safety System
上传时间： 2013-11-14
上传用户：zoudejile
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上传时间： 2013-11-24
上传用户：18707733937
