pci-E电气规格标准
上传时间： 2013-05-26
上传用户：eeworm
月球人的遊戲喔 AMD S3000+ 64Bit $2770 華碩 K8N4-E (pci-E) $3100 華碩 N6200 TC256/128MBTOP $1890 BNEQ 1640 黑/白/銀 $1380 日立 sata 80G/8M 3年保固 $1580 創見DDR400 or 金士頓DDR400 512MB $1490
上传时间： 2013-12-23
上传用户：hustfanenze
DS+DDK+VC开发的适用于PCI、pci-E的驱动程序。
上传时间： 2014-01-19
上传用户：蠢蠢66
pci-E的驱动程序例子,包含基本功能,可用于最初的测试
上传时间： 2016-09-28
上传用户：rocketrevenge
计算机接口通识大全,收集了计算机大部分通用接口,详细介绍我们常用的接口的用途如USB IEEE1394 VGA DVI PCI pci-E S_video 等近百种接口的定义 规格及参数. 在华硕电脑工作快5年了,本人(任PE一职)做笔记本,在网上收集了些资料,自己工作之余做了一下整理,本来是用来给新近员工做基础教育用的,现拿出来分享,同大家一起学习计算机通用接口,有错误之处还请大家到本人网站留言指出,谢谢!
上传时间： 2017-03-29
上传用户：ghostparker
pci-E接口设计是现在系统设计的热点，本文档是在xilinx芯片中集成pcie接口控制器的好资料
上传时间： 2017-08-14
上传用户：yoleeson
RTL8111E是瑞昱的pci-E接口千兆以太网芯片。引脚从48个，外围电路简单，不需要外部EEPROM，MAC地址烧写更加方便。
上传时间： 2021-12-11
上传用户：jiabin
基于SPARTAN-6的pci-E开发板原理图
上传时间： 2022-06-18
上传用户：lipengxu
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2014-01-24
上传用户：s363994250
