The pcI Special Interest Group disclaims all warranties and liability for the use of this document
and the information contained herein and assumes no responsibility for any errors that may appear
in this document, nor does the pcI Special Interest Group make a commitment to update the
information contained herein.
This paper describes a bus mastering implementation of the pcI Express protocol using a Xilinx FPGA. While the theoretical peak performance of pcI Express is quite high, attaining that performance is a complex endeavor on top of an already complex protocol. The implementation is described and its performance is analyzed. Source code is offered for free download via the web.
