LCD显示屏驱动
上传时间： 2021-12-17
上传用户：fliang
此为ISO 7176-21的标准，Requirements and test methods forelectromagnetic compatibility ofelectrically powered wheelchairs andscooters, and battery chargers
标签： iso
上传时间： 2021-12-17
上传用户：
include<reg52.h> #define uint unsigned int #define uchar unsigned char uint temp,aa,wang,qian,bai,shi,ge; sbit dula=P2^6; sbit wela=P2^7; uchar code table[]={ 0x3f,0x06,0x5b,0x4f, 0x66,0x6d,0x7d,0x07, 0x7f,0x6f,0x77,0x7c, 0x39,0x5e,0x79,0x71}; void display( uint wang,uint qian,uint bai,uint shi,uint ge); void delay(uint z); void init(); void main() { init();//初始化子程序 while(1) { if(aa==20) { aa=0; temp++; if(temp==99999) { temp=0; } wang=temp/10000; qian=(temp-wang*10000)/1000; bai=(temp-wang*10000-qian*1000)/100; shi=(temp-wang*10000-qian*1000-bai*100)/10; ge=temp%10; } display(wang,qian, bai,shi,ge); } } void delay(uint z) { uint x,y; for(x=z;x>0;x--) for(y=110;y>0;y--); } void display(uint wang,uint qian,uint bai,uint shi,uint ge) { dula=1; P0=table[wang]; dula=0; P0=0xff; wela=1; P0=0xfe; wela=0; delay(1); dula=1; P0=table[qian]; dula=0; P0=0xff; wela=1; P0=0xfd; wela=0; delay(1); dula=1; P0=table[bai]; dula=0; P0=0xff; wela=1; P0=0xfb; wela=0; delay(1); dula=1; P0=table[shi]; dula=0; P0=0xff; wela=1; P0=0xf7; wela=0; delay(1); dula=1; P0=table[ge]; dula=0; P0=0xff; wela=1; P0=0xef; wela=0; delay(1); } void init() { wela=0; dula=0; temp=0; TMOD=0x01; TH0=(65536-50000)/256; TL0=(65536-50000)%256; EA=1; ET0=1; TR0=1; } void timer0() interrupt 1 { TH0=(65536-50000)/256; TL0=(65536-50000)%256; aa++; } include<reg52.h> #define uint unsigned int #define uchar unsigned char uint temp,aa,wang,qian,bai,shi,ge; sbit dula=P2^6; sbit wela=P2^7; uchar code table[]={ 0x3f,0x06,0x5b,0x4f, 0x66,0x6d,0x7d,0x07, 0x7f,0x6f,0x77,0x7c, 0x39,0x5e,0x79,0x71}; void display( uint wang,uint qian,uint bai,uint shi,uint ge); void delay(uint z); void init(); void main() { init();//初始化子程序 while(1) { if(aa==20) { aa=0; temp++; if(temp==99999) { temp=0; } wang=temp/10000; qian=(temp-wang*10000)/1000; bai=(temp-wang*10000-qian*1000)/100; shi=(temp-wang*10000-qian*1000-bai*100)/10; ge=temp%10; } display(wang,qian, bai,shi,ge); } } void delay(uint z) { uint x,y; for(x=z;x>0;x--) for(y=110;y>0;y--); } void display(uint wang,uint qian,uint bai,uint shi,uint ge) { dula=1; P0=table[wang]; dula=0; P0=0xff; wela=1; P0=0xfe; wela=0; delay(1); dula=1; P0=table[qian]; dula=0; P0=0xff; wela=1; P0=0xfd; wela=0; delay(1); dula=1; P0=table[bai]; dula=0; P0=0xff; wela=1; P0=0xfb; wela=0; delay(1); dula=1; P0=table[shi]; dula=0; P0=0xff; wela=1; P0=0xf7; wela=0; delay(1); dula=1; P0=table[ge]; dula=0; P0=0xff; wela=1; P0=0xef; wela=0; delay(1); } void init() { wela=0; dula=0; temp=0; TMOD=0x01; TH0=(65536-50000)/256; TL0=(65536-50000)%256; EA=1; ET0=1; TR0=1; } void timer0() interrupt 1 { TH0=(65536-50000)/256; TL0=(65536-50000)%256; aa++; } include<reg52.h> #define uint unsigned int #define uchar unsigned char uint temp,aa,wang,qian,bai,shi,ge; sbit dula=P2^6; sbit wela=P2^7; uchar code table[]={ 0x3f,0x06,0x5b,0x4f, 0x66,0x6d,0x7d,0x07, 0x7f,0x6f,0x77,0x7c, 0x39,0x5e,0x79,0x71}; void display( uint wang,uint qian,uint bai,uint shi,uint ge); void delay(uint z); void init(); void main() { init();//初始化子程序 while(1) { if(aa==20) { aa=0; temp++; if(temp==99999) { temp=0; } wang=temp/10000; qian=(temp-wang*10000)/1000; bai=(temp-wang*10000-qian*1000)/100; shi=(temp-wang*10000-qian*1000-bai*100)/10; ge=temp%10; } display(wang,qian, bai,shi,ge); } } void delay(uint z) { uint x,y; for(x=z;x>0;x--) for(y=110;y>0;y--); } void display(uint wang,uint qian,uint bai,uint shi,uint ge) { dula=1; P0=table[wang]; dula=0; P0=0xff; wela=1; P0=0xfe; wela=0; delay(1); dula=1; P0=table[qian]; dula=0; P0=0xff; wela=1; P0=0xfd; wela=0; delay(1); dula=1; P0=table[bai]; dula=0; P0=0xff; wela=1; P0=0xfb; wela=0; delay(1); dula=1; P0=table[shi]; dula=0; P0=0xff; wela=1; P0=0xf7; wela=0; delay(1); dula=1; P0=table[ge]; dula=0; P0=0xff; wela=1; P0=0xef; wela=0; delay(1); } void init() { wela=0; dula=0; temp=0; TMOD=0x01; TH0=(65536-50000)/256; TL0=(65536-50000)%256; EA=1; ET0=1; TR0=1; } void timer0() interrupt 1 { TH0=(65536-50000)/256; TL0=(65536-50000)%256; aa++; }
标签： 矩阵式键盘
上传时间： 2021-12-18
上传用户：2590813506
静力学基础这是一份非常不错的资料，欢迎下载，希望对您有帮助！
标签： 静力学
上传时间： 2021-12-18
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基于FPGA设计的字符VGA LCD显示实验Verilog逻辑源码Quartus工程文件+文档说明,通过字符转换工具将字符转换为 8 进制 mif 文件存放到单端口的 ROM IP 核中，再从ROM 中把转换后的数据读取出来显示到 VGA 上，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上传时间： 2021-12-18
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基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
标签： fpga sdram verilog quartus
上传时间： 2021-12-18
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基于FPGA设计的vga显示测试实验Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r = video_r[7:3]; //discard low bit dataassign vga_out_g = video_g[7:2]; //discard low bit dataassign vga_out_b = video_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule
标签： fpga vga显示 verilog quartus
上传时间： 2021-12-19
上传用户：kingwide
FPGA片内FIFO读写测试Verilog逻辑源码Quartus工程文件+文档说明，使用 FPGA 内部的 FIFO 以及程序对该 FIFO 的数据读写操作。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz时钟 input rst_n //复位信号，低电平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO写数据wire wr_en; //FIFO写使能wire rd_en; //FIFO读使能wire[15:0] r_data; //FIFO读数据wire full; //FIFO满信号 wire empty; //FIFO空信号 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///产生FIFO写入的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空， 开始写FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO满 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///产生FIFO读的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO满, 开始读FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)
上传时间： 2021-12-19
上传用户：20125101110
“电路计算器”是工程师的离线电子设计工具。本软件适用于Android平台具有便利性，可见性以及在最短时间内找到最佳解决方案的能力。超过130个模拟电路拓扑，超过40个电子计算器，超过20个应用笔记，逻辑求解器。特征：*电流源和接收器。*低通，高通，带通，带阻滤波器。*数学运算。*电源电路。*开关电源模块。*控制回路补偿。
上传时间： 2021-12-19
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常用继电器类PCB封装库Altium封装库三维视图PCB库(3D封装库合集),76个封装，PcbLibb后缀文件，封装列表如下：Component Count : 76Component Name-----------------------------------------------0MI-SH-112LM012-1HW_BK012-1HW_W012-1ZW_BK012-1ZW_W855AWP-1A-C2892-1CC-C892N-1AC-CATQ203DSP1DSP2G4A-1A-E-CNG5NB-1A-E-5VG6K-2F-YHF46-xx-HS1HF163F-LHFD3-DIPHFD3-SMDHK19F-DCHK4100FHRS1HHRS2HJDQ-12V30AJDQ-793-PJDQ-835-1AJDQ-842-1JDQ-4078-2CJDQ-EC2-12NUJDQ-G5V-1JDQ-WJ112-1CJQX-14FC-1A_BKJQX-14FC-1A_WJQX-14FC-1AH_BKJQX-14FC-1AH_WJQX-14FC-1B_BKJQX-14FC-1B_WJQX-14FC-1BH_BKJQX-14FC-1BH_WJQX-14FC-1C_BKJQX-14FC-1C_WJQX-14FC-1CH_BKJQX-14FC-1CH_WJQX-14FC-2A_BKJQX-14FC-2A_WJQX-14FC-2B_BKJQX-14FC-2B_WJQX-14FC-2C_BKJQX-14FC-2C_WJQX-105F-2JZC-23F(4123)JZC-32F_1HJZC-32F_1ZK1MKT6-S-12DHOJ-SH-112LMHOJE-SS-112DMOMI-SH-112LMOMIF-S-112LMOZ-SS-112LOZ-SS-112LM1PCJRelay-1A0500SDT-S-112DMRSIL24-1A72-71DSLA-xxVDC-SL-ASPA-S-112DMSRD-A_BSRD-A_BKSRD-A_YSRD-B_BSRD-B_BKSRD-B_YSRD-C_BSRD-C_BKSRD-C_YTA-1a
上传时间： 2021-12-21
上传用户：bluedrops
