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multi-characteristics

  • 基于DSP的新型柴油发电机励磁控制系统研究

    在综合分析谐波励磁无刷同步发电机励磁控制系统的基础上,对其励磁控制策略进行了研究,开发了一套基于DSP( TMS320F2812) 控制的新型柴油发电机励磁控制系统,该系统采用参数自适应模糊PID 控制励磁,选用交流采样方式实时检测各信号的瞬时特性,系统仿真结果以及在1 台25 kW 工频柴油发电机上的试验结果证明了该控制器具有较好的电压调节特性,系统稳态和暂态性能完全满足发电机对励磁系统的要求。关键词:励磁调节;模糊PID 控制;数字信号处理器;交流采样 Abstract :According to the general analysis of the excitation cont rol system of the harmonious wave excitation brushless synchronous generator and it s characteristics ,a new type of diesel generator excitation cont rol system based on DSP( TMS320F2812) was designed. An adaptive fuzzy PID cont rol of excitation is used in this system. To detect the t ransient characteristics of the signals in a timely manner ,AC sampling was applied.The system simulation result s and the testing result s f rom a 25 kW diesel generator (50 Hz) can prove that the voltage regulation characteristics of the excitation cont rol system are very well ,and both the steadyOstate performance and the t ransient performance of the generator are also good.Key words :excitation cont rol ;fuzzy PID cont rol ;digital signal processor (DSP) ;AC sampling

    标签: DSP 柴油发电机 励磁控制 系统研究

    上传时间: 2013-10-29

    上传用户:fxf126@126.com

  • Xilinx UltraScale:新一代架构满足您的新一代架构需求(EN)

      中文版详情浏览:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    标签: UltraScale Xilinx 架构

    上传时间: 2013-11-13

    上传用户:瓦力瓦力hong

  • 基于以太网的虚拟示波器设计

    为提升虚拟仪器传输速率与实时性能,扩展监测范围,在VC的软件平台上设计了一种全功能虚拟示波器。与传统虚拟示波器相比,该系统采用嵌入式系统完成信号采集,采用工业以太网为传输介质,通过线性插值算法和多线程编程思想,实现波形显示、参数计算、频谱分析以及波形存储及回放功能。实验结果表明,该虚拟示波器可以实现20 kHz采样频率下的波形精确显示,达到预期的各项指标。 Abstract:  o enhance the transfer rate and real-time of virtual instrument performance, expand scope of monitoring, this paper uses the VCs software platform to design a fully functional virtual oscilloscope. Compared with traditional virtual oscilloscope, this system adopts the embedded system to complete the data acquisition, industrial Ethernet as the transmission medium used by the linear interpolation algorithm and multi-threaded programming ideas, namely to achieve waveform display, parameter calculation, spectrum analysis and waveform storage and playback. Experimental results show that the virtual oscilloscope can accurately display the waveform with 20kHz sampling frequency, and achieve the desired targets.

    标签: 以太网 虚拟 波器设计

    上传时间: 2013-11-25

    上传用户:wbwyl

  • 无线电设计入门资料

    Abstract: The process of designing a radio system can be complex and often involves many project tradeoffs. Witha little insight, balancing these various characteristics can make the job of designing a radio system easier. Thistutorial explores these tradeoffs and provides details to consider for various radio applications. With a focus on theindustrial, scientific, medical (ISM) bands, the subjects of frequency selection, one-way versus two-way systems,modulation techniques, cost, antenna options, power-supply influences, effects on range, and protocol selectionare explored.

    标签: 无线

    上传时间: 2013-12-13

    上传用户:eastgan

  • 基于塑料光纤的高压隔离通信接口设计

     通过比较各种隔离数字通信的特点和应用范围,指出塑料光纤在隔离数字通信中的优势。使用已经标准化的TOSLINK接口,有利于节省硬件开发成本和简化设计难度。给出了塑料光纤的硬件驱动电路,说明设计过程中的注意事项,对光收发模块的电压特性和频率特性进行全面试验,并给出SPI口使用塑料光纤隔离通信的典型应用电路图。试验结果表明,该设计可为电力现场、电力电子及仪器仪表的设计提供参考。 Abstract:  y comparing characteristics and applications area of various isolated digital communications, this article indicates advantages of plastic optical fiber in isolated digital communications. Using the standardized TOSLINK interface, it helps to control costs and difficulty in hardware development and design. Then it gives the hardware driver circuit of plastic optical fiber module, explains the noticed details in design process, gives results on the basis of the optical transceiver module voltage characteristics and frequency characteristics tests. Finally,it gives typical application circuit of the SPI communication port by using plastic optical fiber isolation .The results show that this design can be referenced for the power field, power electronics and instrumentation design.

    标签: 塑料光纤 高压隔离 通信 接口设计

    上传时间: 2014-01-10

    上传用户:gundan

  • 快速跳频通信系统同步技术研究

    同步技术是跳频通信系统的关键技术之一,尤其是在快速跳频通信系统中,常规跳频通信通过同步字头携带相关码的方法来实现同步,但对于快跳频来说,由于是一跳或者多跳传输一个调制符号,难以携带相关码。对此引入双跳频图案方法,提出了一种适用于快速跳频通信系统的同步方案。采用短码携带同步信息,克服了快速跳频难以携带相关码的困难。分析了同步性能,仿真结果表明该方案同步时间短、虚警概率低、捕获概率高,同步性能可靠。 Abstract:  Synchronization is one of the key techniques to frequency-hopping communication system, especially in the fast frequency hopping communication system. In conventional frequency hopping communication systems, synchronization can be achieved by synchronization-head which can be used to carry the synchronization information, but for the fast frequency hopping, Because modulation symbol is transmitted by per hop or multi-hop, it is difficult to carry the correlation code. For the limitation of fast frequency hopping in carrying correlation code, a fast frequency-hopping synchronization scheme with two hopping patterns is proposed. The synchronization information is carried by short code, which overcomes the difficulty of correlation code transmission in fast frequency-hopping. The performance of the scheme is analyzed, and simulation results show that the scheme has the advantages of shorter synchronization time, lower probability of false alarm, higher probability of capture and more reliable of synchronization.

    标签: 快速跳频 同步技术 通信系统

    上传时间: 2013-11-23

    上传用户:mpquest

  • LPC315x系列ARM微控制器用户手册

    The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.

    标签: 315x LPC 315 ARM

    上传时间: 2014-01-17

    上传用户:Altman

  • 时钟恢复设计_英文版

    Today in many applications such as network switches, routers, multi-computers,and processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.

    标签: 时钟恢复 英文

    上传时间: 2013-10-30

    上传用户:ysjing

  • H-JTAG调试软件下载

    ARM通讯   H-JTAG 是一款简单易用的的调试代理软件,功能和流行的MULTI-ICE 类似。H-JTAG 包括两个工具软件:H-JTAG SERVER 和H-FLASHER。其中,H-JTAG SERVER 实现调试代理的功能,而H-FLASHER则实现了FLASH 烧写的功能。H-JTAG 的基本结构如下图1-1所示。  H-JTAG支持所有基于ARM7 和ARM9的芯片的调试,并且支持大多数主流的ARM调试软件,如ADS、RVDS、IAR 和KEIL。通过灵活的接口配置,H-JTAG 可以支持WIGGLER,SDT-JTAG 和用户自定义的各种JTAG 调试小板。同时,附带的H-FLASHER 烧写软件还支持常用片内片外FLASH 的烧写。使用H-JTAG,用户能够方便的搭建一个简单易用的ARM 调试开发平台。H-JTAG 的功能和特定总结如下: 1. 支持 RDI 1.5.0 以及 1.5.1; 2. 支持所有ARM7 以及 ARM9 芯片; 3. 支持 THUMB 以及ARM 指令; 4. 支持 LITTLE-ENDIAN 以及 BIG-ENDIAN; 5. 支持 SEMIHOSTING; 6. 支持 WIGGLER, SDT-JTAG和用户自定义JTAG调试板; 7. 支持 WINDOWS 9.X/NT/2000/XP; 8.支持常用FLASH 芯片的编程烧写; 9. 支持LPC2000 和AT91SAM 片内FLASH 的自动下载;

    标签: H-JTAG 调试软件

    上传时间: 2014-12-01

    上传用户:Miyuki

  • Xilinx UltraScale:新一代架构满足您的新一代架构需求(EN)

      中文版详情浏览:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    标签: UltraScale Xilinx 架构

    上传时间: 2013-11-21

    上传用户:wxqman