VHDL代码风格和常见的语法错误分析
上传时间: 2013-10-18
上传用户:KSLYZ
01_Altera器件的推荐代码风格
上传时间: 2013-10-31
上传用户:瓦力瓦力hong
SOPC嵌入式系统实验教程(一)【作者:周立功;出版社:北京航空航天大学出版社】(因网上资料有限,所以本资料为周立功 SOPC嵌入式系统实验教程(一)部分章节及实验代码,真心想学的可以买一本书看看。) 该书是与《SOPC嵌入式系统基础教程》相配套的实验教材。设计开发了 45个实验,包括SOPC硬件系统的基础实验,基于Nios II外设的基础编程实验,基于实验箱外设的Nios II高级编程实验,在Nios II系统中进行基于μ C/OS-II操作系统的应用程序开发实验和SOPC硬件系统的高级实验。各种实验的安排由浅人深,由硬件到软件,相对完整,使读者很容易学习和掌握SO PC嵌入式系统的开发应用。
上传时间: 2013-11-01
上传用户:superman111
FIFO的verilog代码
上传时间: 2013-12-22
上传用户:ccxzzhm
ZBT SRAM控制器参考设计,xilinx提供VHDL代码 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.
上传时间: 2013-10-25
上传用户:peterli123456
USB接口控制器参考设计,xilinx提供VHDL代码 usb xilinx vhdl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
上传时间: 2013-10-29
上传用户:zhouchang199
ref-sdr-sdram-vhdl代码 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上传时间: 2013-10-23
上传用户:半熟1994
UART 4 UART参考设计,Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
上传时间: 2013-11-02
上传用户:18862121743
ACS400报警代码
上传时间: 2014-07-11
上传用户:13215175592
实验c语言代码,想看就看啦
上传时间: 2013-11-15
上传用户:asdstation