Builder uses to integrate a larger system module. Each component consists of a structured set of files within a directory. The files in a component directory serve the following The RS232 UART Core implements a method for communication of serial data. The core provides a simple register-mapped Avalon庐 interface. Master peripherals [such as a Nios庐 II processor] communicate with the core by reading and writing control and data registers.
标签： structured integrate component consists
上传时间： 2014-01-15
上传用户：lnnn30
In the bank all the activities are being done manually .As the bank widens its services & it finds difficult to manage its operations manually and hence this leads to the automation of some of its operations. Banking Information system is a windows based applications. This project mainly deals with managing there types of account such as Saving Account, Current Account and Recurring Deposits . In this project bank is seeking to manage these account through computer based system. Tasks involved in this project are opening the user accounts , recording the account holders transactions , modify, the user records and generating the reports . This project is having three module: ] 1. Bank Master Module 2. Transaction Module 3. Reports module
标签： the bank activities manually
上传时间： 2013-12-13
上传用户：LouieWu
利用并行技术，动态的完成图的绘制，当slave完成一行的绘制，master会自动给出另一行的序号
标签： 并行技术
上传时间： 2017-04-16
上传用户：maizezhen
python 中文显示，py chinese
标签： python
上传时间： 2017-05-11
上传用户：leehom61
一个不错的modbus源码，含有master和slave两部分
上传时间： 2017-06-04
上传用户：253189838
I always believe that one will easily lag behind unless he keeps on learning. Of course, if I am given a chance for advanced studies in this famous University , I will stare to effort to master a good command of advance my capability.
标签： learning believe always behind
上传时间： 2017-06-13
上传用户：极客
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
标签： Tensilica OpenCores interface the
上传时间： 2013-12-21
上传用户：gonuiln
This document gives the code for programming a CC2500 transceiver using Altera Stratix FPGA. The FPGA and CC2500 are connected through SPI mode with the FPGA as the master and CC2500 as the slave.
标签： programming transceiver document Stratix
上传时间： 2014-01-15
上传用户：wuyuying
jamod is an object oriented implementation of the Modbus protocol, realized 100 in Java. It allows to quickly realize master and slave applications in various transport flavors (IP and serial).
标签： implementation oriented protocol realized
上传时间： 2017-07-17
上传用户：LouieWu
In this work an implementation of a geometric nonlinear controller for chaos synchronization in a Field Programmable Gate Array (FPGA) is presented. The Lorenz chaotic system is used to show the implementation of chaos synchronization via nonlinear controller implemented in a Xilinx FPGA Virtex-II 2v2000ft896-4. The main idea is to design a nonlinear geometric controller which synchronizes a slave Lorenz system to a master system and then implement them into the FPGA.
标签： synchronization implementation controller geometric
上传时间： 2013-12-17
上传用户：3到15
