摘 要:用一种新的思路和方法,先计算低通、再计算高通滤波器的有关参数,然后组合成带通滤波器.关键词:滤波器;参数;新思路中图分类号: TN713. 5 文献识别码:B 文章编号:1008 - 1666 (1999) 04 - 0089 - 03A New Consideration of the Band Filter’s CalculationGuo Wencheng( S hao Yang B usiness and Technology school , S haoyang , Hunan ,422000 )Abstract :This essay deals with a new method of calculating the band filters - first calculatingthe relevant parameters of low - pass filters ,then calculating the ones of high - pass filters.Key words :filter ; parameters ;new considercation八十年代后,信息产业得到了迅猛发展. 带通滤波器在微波通信、广播电视和精密仪器设备中得到了广泛应用. 带通滤波器性能的优劣,对提高接收机信噪比,防止邻近信道干扰,提高设备的技术指标,有着十分重要的意义.我在长期的教学实践中,用切比雪夫型方法设计、计算出宽带滤波器集中参数元件的数据. 该滤波器可运用在检测微波频率的仪器和其他设备中. 再将其思路和计算方法介绍给大家,供参考.
上传时间： 2014-12-28
上传用户：Yukiseop
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded controlapplications.
上传时间： 2013-11-10
上传用户：1427796291
针对使用硬件描述语言进行设计存在的问题，提出一种基于FPGA并采用DSP Builder作为设计工具的数字信号处理器设计方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ设计流程，设计了一个12阶FIR 低通数字滤波器，通过Quartus 时序仿真及嵌入式逻辑分析仪SignalTapⅡ硬件测试对设计进行了验证。结果表明，所设计的FIR 滤波器功能正确，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
上传时间： 2013-11-17
上传用户：lo25643
针对运行中火车测速运用多普勒效应采用DSP 设计雷达测速系统并阐述了其基本设计思想与工作原理给出系统硬件软件设计结构和原理图改善了原有光电测速精度提高了系统工作稳定性和可靠性经实验证明DSP 采集板工作稳定测速效果好关键词DSP; 雷达测速; 多普勒效应 On Board DSP-Based Radar Speed Measurement System TANG Wei, SUN Zhi-fang, CHEN Quan (Dept.of computer Science,Yangtze University,Jingzhou 434023,China)Abstract: This paper presents a DSP-based train speed measurement by using Doppler radar. The structure of the system is introduced.The hardware and software are also discussed.Key words: DSP; rader speed measurement; doppler principle
上传时间： 2013-10-27
上传用户：003030
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-sensitive markets. Application classes like
上传时间： 2013-11-10
上传用户：XLHrest
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
标签： PicoBlaze Create Master Xilinx
上传时间： 2013-11-05
上传用户：a6697238
Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
标签： Solutions Analog Xilinx FPGAs
上传时间： 2013-11-01
上传用户：a67818601
Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)
标签： Solutions Analog Altera FPGAs
上传时间： 2013-11-08
上传用户：虫虫虫虫虫虫
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上传时间： 2014-08-16
上传用户：adada
