kbyte

200-MHz ARM920T Processor • 16-kbyte Instruction Cache • 16-kbyte Data Cache •

200-MHz ARM920T Processor • 16-kbyte Instruction Cache • 16-kbyte Data Cache • Linux® , Microsoft® Windows® CE-enabled MMU • 100-MHz System Bus • MaverickCrunch™ Math Engine • Floating Point, Integer, and Signal Processing Instructions • Optimized for digital music compression and decompression algorithms. • Hardware interlocks allow in-line coding. • MaverickKey™ IDs • 32-bit Unique ID can be used for DRM-compliant 128-bit random ID. • Integrated Peripheral Interfaces • 32-bit SDRAM Interface

标签： 8226 Cache kbyte Instruction

上传时间： 2017-04-08

上传用户：comua
介绍几种cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducin

介绍几种cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducing the advanced register based CPU architecture i.e., the MCS 251 microcontroller architecture. The register based CPU supports a 40-byte register file. In addition, the 8xC251SA/SB/SP/SQ microcontroller has 256-kbyte expanded external code/data memory space and 64-kbyte stack space. The new controller is also specially designed to execute C code efficiently. More importantly, the 8xC251SA/SB/SP/SQ maintains binary code compatibility with MCS 51 microcontrollers but at the same time allows the use of the powerful MCS 251 microcontroller instruction set, with many new 8, 16 and 32 bit instructions available. The 8xC251SA/SB/SP/SQ has 512 bytes or 1 kbyte of on-chip data RAM options and is available in 16 kbytes and 8 kbytes of on-chip ROM/OTPROM or ROMless options.

标签： architecture introducin peripheral improves

上传时间： 2015-03-15

上传用户：ccclll
STM8S003参考手册

意法半导体STM8系列参考手册Program memory: 8 kbyte Flash memory; dataretention 20 years at 55 °C after 100 cycles• RAM: 1 kbyte• Data memory: 128 bytes true data EEPROM;endurance up to 100 k write/erase cycles

标签： stm8

上传时间： 2022-04-27

上传用户：zhaiyawei