mpeg test inter b. Dequantizer Algorithm hardware realization method and comparison c. Dequantizer Hardware Architecture Design
标签： b. c. Dequantizer realization
上传时间： 2016-01-29
上传用户：450976175
描述Serv-UFTP建立和维护手册，对那些刚接触FTP网友，特别是自己刚架设FTP的个人FTP管理员有帮助
标签： Serv-UFTP
上传时间： 2014-08-05
上传用户：mpquest
I2C（Inter-IC）总线10多年前由Philips公司推出，是近年来在微电子通信控制领域广泛采用的一种新型总线标准。
上传时间： 2013-12-02
上传用户：dianxin61
Inter接口技术微处理器应用第一到2章
上传时间： 2016-07-13
上传用户：1051290259
基于AR模型的间谐波检测算法的研究Based on the model of inter-AR harmonic detection algorithm research
标签： detection algorithm inter-AR harmonic
上传时间： 2016-07-16
上传用户：silenthink
飞思卡尔S12系列Inter-IC_Bus__(IIC)应用范例
标签： Inter-IC_Bus S12 IIC 飞思卡尔
上传时间： 2014-01-02
上传用户：bruce5996
一个用Inter汇编写的电话薄程序，可以作为新手学习的参考。主要是结构体和数组指针的应用。
上传时间： 2013-12-31
上传用户：silenthink
Inter-Chip USB Supplement to the USB 2.0 Specification_1.0.pdf
标签： Specification Inter-Chip Supplement USB
上传时间： 2014-01-08
上传用户：GHF
Serv-U7.0.0.4 carck Serv-U7.0.0.4 carck
上传时间： 2013-12-26
上传用户：qiaoyue
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
标签： bus bidirectional primarily designed
上传时间： 2013-12-11
上传用户：jeffery
