This simple simulation of a pulse traveling down a parallel-plate guide makes a handy test code for initial experiments with boundary conditions. ToyFDTD3 adds some simple features to ToyFDTD1: A PMC boundary condition, a sinusoidal pulse source, and output tracking a single point in the mesh. Released 15 June 1999.
标签： parallel-plate simulation traveling simple
上传时间： 2015-04-06
上传用户：stella2015
RLC Test程序,一个电子竞赛的题目。里面有详尽的源代码。
上传时间： 2013-12-22
上传用户：czl10052678
The purpose of this computer program is to allow the user to construct, train and test differenttypes of artificial neural networks. By implementing the concepts of templates, inheritance andderived classes from C++ object oriented programming, the necessity for declaring multiple largestructures and duplicate attributes is reduced. Utilizing dynamic binding and memory allocationafforded by C++, the user can choose to develop four separate types of neural networks:
标签： differenttype construct computer purpose
上传时间： 2013-12-06
上传用户：13517191407
HCI test in bluetooth in WINCE
上传时间： 2014-12-03
上传用户：541657925
use dsp5402 dram to let green led flashing in order to test dsp
上传时间： 2015-04-16
上传用户：zhangyi99104144
CH372 Driver Program,for reference only,test file
标签： reference Program Driver file
上传时间： 2014-01-08
上传用户：咔乐坞
TEST.C是在ARM的Web Server源文件，现在用VB实现，用来分析TCPIP。
上传时间： 2013-12-20
上传用户：daoxiang126
test for boundary scan and CPLD ics.
上传时间： 2014-01-17
上传用户：songnanhua
这篇文章主要介绍ARM JTAG调试的基本原理。基本的内容包括了TAP (TEST ACCESS PORT) 和BOUNDARY-SCAN ARCHITECTURE的介绍，在此基础上，结合ARM7TDMI详细介绍了的JTAG调试原理。
标签： BOUNDARY-SCAN ARCHITECTURE ACCESS JTAG
上传时间： 2014-01-22
上传用户：ddddddos
Lattice公司的A Verilog HDL Test Bench Primer应用手册
标签： Lattice Verilog Primer Bench
上传时间： 2015-04-25
上传用户：宋桃子
