基于Verilog-HDL的硬件电路的实现 9.7 步进电机的控制 9.7.1 步进电机驱动的逻辑符号 9.7.2 步进电机驱动的时序图 9.7.3 步进电机驱动的逻辑框图 9.7.4 计数模块的设计与实现 9.7.5 译码模块的设计与实现 9.7.6 步进电机驱动的Verilog-HDL描述 9.7.7 编译指令-"宏替换`define"的使用方法 9.7.8 编译指令-"时间尺度`timescale"的使用方法 9.7.9 系统任务-"$finish"的使用方法 9.7.10 步进电机驱动的硬件实现
标签： Verilog-HDL 步进电机驱动 9.7 硬件电路
上传时间： 2014-01-23
上传用户：拔丝土豆
Jode Decompiler.安装方法：点击Eclipse的Help菜单 --> Software Updates --> Find and install...，然后选择：Search for new features to install，在弹出的对话框中点击"New Remote Site..."菜单。填入：Name: Jode DecomopilerURL: http://www.technoetic.com/eclipse/update点击"finish"。之后可以在Window菜单的Preferences --> Java -->Jode Decompiler中配置插件的信息。
标签： Decompiler Software Eclipse Updates
上传时间： 2015-11-19
上传用户：cuibaigao
First of all we would like to thank God Almighty for giving us the strength and confidence in pursing the ambitions. We would like to thank our Examiner Professor Axel Jantsch for allowing us to do this under his guidance and encouragement. At the same time we would like to mention our sincere thanks to Mr. Said Zainali, Manager of FRAME ACCESS AB for giving all the required equipment and the technical support which helped us to finish this thesis. We would like to mention our gratitude to our fellow VACS team members who helped us a lot during difficult times.
标签： confidence Almighty strength giving
上传时间： 2013-12-01
上传用户：小码农lz
看n2实例 #Create a simulator object set ns [new Simulator] #Define different colors for data flows #$ns color 1 Blue #$ns color 2 Red #Open the nam trace file set nf [open out-1.nam w] $ns namtrace-all $nf set f0 [open out0.tr w] set f1 [open out1.tr w] #Define a finish procedure proc finish {} { global ns nf $ns flush-trace #Close the trace file close $nf #Execute nam on the trace file exit 0 } #Create four nodes set n0 [$ns node] set n1 [$ns node] set n2 [$ns node] set n3 [$ns node] #Create links between the nodes $ns duplex-link $n0 $n2 1Mb 10ms
标签： simulator Simulator different Create
上传时间： 2016-07-02
上传用户：wfl_yy
SOPC实验--Hello World实验:启动Quartus II软件，选择File→New Project Wizard，在出现的对话框中填写项目名称 2、 点击finish，然后选择“是”。选择Assignments→Device，改写各项内容。Family改为CycloneII，根据实验板上的器件选择相应的器件，本实验选择EP2C5T144C8,点击对话框中的Device & Pin Options，在Configuration中，选项Use Configuration Device为EPCS1，选项Unused Pins为As inputs,tri-stated.
上传时间： 2014-01-13
上传用户：梧桐
在采用多道程序设计的系统中，往往有若干个进程同时处于就绪状态。当就绪进程个数大于处理机数时，就必须依照某种策略来决定哪些进程优先占用处理机。本实验模拟在单处理机情况下的处理机调度，帮助学生加深了解处理机调度的工作。 二、实验类型 设计型。 三、预习内容 预习课本处理机调度有关内容，包括进程占用处理机的策略方法。 四、实验要求与提示 设计进程调度算法，进程数不定；包含几种调度算法，并加以实现；输出进程的调度过程——进程的状态、链表等。要求使用优先权法和轮转法模拟进程调度过程。 【提示】：简化假设 1） 进程为计算型的（无I/O） 2） 进程状态：ready、running、finish 3） 进程需要的CPU时间以时间片为单位确定 【提示】：算法描述 1） 优先权法——动态优先权，当前运行进程用完时间片后，其优先权减去一个常数。 2） 轮转法
上传时间： 2013-12-15
上传用户：duoshen1989
Learn how to leverage a key Java technology used to access relational data from Java programs, in an Oracle environment. Author Donald Bales begins by teaching you the mysteries of establishing database connections, and how to issue SQL queries and get results back. You ll move on to advanced topics such as streaming large objects, calling PL/procedures, and working with Oracle9i s object-oriented features, then finish with a look at transactions, concurrency management, and performance
标签： Java technology relational leverage
上传时间： 2017-08-02
上传用户：xz85592677
Using Trolltech s Qt you can build industrial-strength C++ applications that run natively on Windows, Linux/Unix, Mac OS X, and embedded Linux--without making source code changes. With this book Trolltech insiders have written a start-to-finish guide to getting great results with the most powerful version of Qt ever created: Qt 4.1.
标签： industrial-strength applications Trolltech natively
上传时间： 2017-08-11
上传用户：邶刖
The running time of quicksort can be improved in practice by taking advantage of the fast running time of insertion sort when its input is “nearly” sorted. When quicksort is called on a subarray with fewer than k elements, let it simply return without sorting the subarray. After the top-level call to quicksort returns, run insertion sort on the entire array to finish the sorting process.
标签： running advantage quicksort improved
上传时间： 2013-12-01
上传用户：梧桐
基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
标签： fpga sdram verilog quartus
上传时间： 2021-12-18
上传用户：
