The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
上传时间： 2013-10-09
上传用户：3294322651
The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-active noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.
标签： MULTICHANNEL 5.5 TO RS
上传时间： 2013-10-19
上传用户：ddddddd
关键词 PCI的总线协议，数据传输摘 要本文档介绍通过 Actel Flash 的FPGA 来实现PCI 的桥接芯片的功能
上传时间： 2013-10-08
上传用户：kongrong
UART测试程序-AT91SAM9260://* The software is delivered "AS IS" without warranty or condition of any//* kind, either express, implied or statutory. This includes without//* limitation any warranty or condition with respect to merchantability or//* fitness for any particular purpose, or against the infringements of//* intellectual property rights of others.
上传时间： 2013-11-18
上传用户：yepeng139
详细阐述一种利用CPLD 实现的8 位单片机与PCI 设备间的通信接口方案，给出用ABEL HDL编写的主要源程序。该方案在实践中检验通过。
上传时间： 2013-10-30
上传用户：yeling1919
Internal Interrupts are used to respond to asynchronous requests from a certain part of themicrocontroller that needs to be serviced. Each peripheral in the TriCore as well as theBus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPUitself can generate an Interrupt Request.So what is an external Interrupt?An external Interrupt is something alike as the internal Interrupt. The difference is that anexternal Interrupt request is caused by an external event. Normally this would be a pulseon Port0 or Port1, but it can be even a signal from the input buffer of the SSC, indicatingthat a service is requested.The User’s Manual does not explain this aspect in detail so this ApNote will explain themost common form of an external Interrupt request. This ApNote will show that there is aneasy way to react on a pulse on Port0 or Port1 and to create with this impulse an InterruptService Request. Later in the second part of the document, you can find hints on how todebounce impulses to enable the use of a simple switch as the input device.Note: You will find additional information on how to setup the Interrupt System in theApNote “First steps through the TriCore Interrupt System” (AP3222xx)1. It would gobeyond the scope of this document to explain this here, but you will find selfexplanatoryexamples later on.
上传时间： 2013-10-27
上传用户：zhangyigenius
通用的多电源总线，如VME、VXI 和PCI 总线，都可提供功率有限的3.3V、5V 和±12V（或±24V）电源，如果在这些系统中添加设备（如插卡等），则需要额外的3.3V或5V电源，这个电源通常由负载较轻的-12V电源提供。图1 电路，将-12V 电压升压到15.3V（相对于-12V 电压），进而得到3.3V 的电源电压，输出电流可达300mA。Q2 将3.3V 电压转换成适当的电压（-10.75V）反馈给IC1 的FB 引脚，PWM 升压控制器可提供1W 的输出功率，转换效率为83%。整个电路大约占6.25Cm2的线路板尺寸，适用于依靠台式PC机电源供电，需要提供1W输出功率的应用，这种应用中，由于-12V总线电压限制在1.2W以内，因此需要保证高于83%的转换效率。由于限流电阻（RSENSE）将峰值电流限制在120mA，N 沟道MOSFET（Q1）可选用廉价的逻辑电平驱动型场效应管，R1、R2 设置输出电压（3.3V 或5V）。IC1 平衡端（Pin5）的反馈电压高于PGND引脚（Pin7）1.25V，因此：VFB = -12V + 1.25V = - 10.75V选择电阻R1后，可确定：I2 = 1.25V / R1 = 1.25V / 12.1kΩ = 103μA可由下式确定R2：R2 = （VOUT - VBE）/ I2 =（3.3V - 0.7V）/ 103μA = 25.2 kΩ图1 中，IC1 的开关频率允许通过外部电阻设置，频率范围为100kHz 至500kHz，有利于RF、数据采集模块等产品的设计。当选择较高的开关频率时，能够保证较高的转换效率，并可选用较小的电感和电容。为避免电流倒流，可在电路中增加一个与R1串联的二极管。
上传时间： 2013-10-17
上传用户：jixingjie
The PL2303 USB to Serial adapter is your smart and convenient accessory forconnecting RS-232 serial devices to your USB-equipped Windows host computer. Itprovides a bridge connection with a standard DB 9-pin male serial port connector inone end and a standard Type-A USB plug connector on the other end. You simplyattach the serial device onto the serial port of the cable and plug the USB connectorinto your PC USB port. It allows a simple and easy way of adding serial connectionsto your PC without having to go thru inserting a serial card and traditional portconfiguration.This USB to Serial adapter is ideal for connecting modems, cellular phones, PDAs,digital cameras, card readers and other serial devices to your computer. It providesserial connections up to 1Mbps of data transfer rate. And since USB does not requireany IRQ resource, more devices can be attached to the system without the previoushassles of device and resource conflicts.Finally, the PL-2303 USB to Serial adapter is a fully USB Specification compliantdevice and therefore supports advanced power management such as suspend andresume operations as well as remote wakeup. The PL-2303 USB Serial cable adapteris designed to work on all Windows operating systems.
上传时间： 2013-11-01
上传用户：ghostparker
PCI Express 协议由于其高速串行、系统拓扑简单等特点被广泛用于各种领域。Altera公司的Arria II GX FPGA内集成了支持链式DMA传输功能的PCI Express硬核，适应了PCI Express总线高速度的要求。文中利用Jungo公司的WinDriver软件实现了链式DMA的上层应用设计。首先给出了链式DMA实现的基本过程，接着分析了链式DMA数据传输需要处理的几个问题，给出了相应的解决办法和策略。采用这些方法，保证了DAM数据传输的正确性，简化了底层FPGA应用逻辑的设计。
上传时间： 2013-11-20
上传用户：hanwudadi
白皮书：采用低成本FPGA实现高效的低功耗PCIe接口 了解一个基于DDR3存储器控制器的真实PCI Express® （PCIe®） Gen1x4参考设计演示高效的Cyclone V FPGA怎样降低系统总成本，同时实现性能和功耗目标。点击马上下载！
上传时间： 2013-11-16
上传用户：huangld
