常用D/A转换器和A/D转换器介绍 下面我们介绍一下其它常用D/A转换器和 A/D 转换器，便于同学们设计时使用。 1. DAC0808 图 1 所示为权电流型 D/A 转换器 DAC0808 的电路结构框图。用 DAC0808 这类器件构 成的 D/A转换器，需要外接运算放大器和产生基准电流用的电阻。DAC0808 构成的典型应用电路如图2 所示。
标签： 转换器
上传时间： 2014-12-23
上传用户：zhenyushaw
Abstract: Most magnetic read head data sheets do not fully specify the frequency-dependent components andare often vague when specifying other key parameters. In some cases, the specifications of two very similarheads from two different manufacturers might be quite different in terms of parameters specified and omitted.The limitations in the data sheets make designing an optimum card reading system unnecessarily difficult andtime consuming. This document outlines a strategy to overcome the above shortcomings and offers guidelinesto overcome the noise issues.
上传时间： 2013-11-13
上传用户：dysyase
isoad系列产品实现传感器和主机之间的信号安全隔离和高精度数字采集与传输，广泛应用于rs-232/485总线工业自动化控制系统，4-20ma / 0-10v信号测量、监视和控制，小信号的测量以及工业现场信号隔离及长线传输等远程监控场合。通过软件的配置，可接入多种传感器类型，包括电流输出型、电压输出型、以及热电偶等等。 产品内部包括电源隔离，信号隔离、线性化，a/d转换和rs-485串行通信等模块。每个串口最多可接256只iso ad系列模块，通讯方式采用ascii 码字符通讯协议或modbus rtu通讯协议，其指令集兼容于adam模块，波特率可由用户设置，能与其他厂家的控制模块挂在同一rs-485总线上，便于主机编程。 isoad系列产品是基于单片机的智能监测和控制系统，所有用户设定的校准值，地址，波特率，数据格式，校验和状态等配置信息都储存在非易失性存储器eeprom里。 isoad系列产品按工业标准设计、制造，信号输入 / 输出之间隔离，可承受3000vdc隔离电压，抗干扰能力强，可靠性高。工作温度范围- 45℃～+80℃。
上传时间： 2013-11-23
上传用户：comer1123
This document and the associated reference design provide guidance for assigning anddebugging software to or in FLASH memory, specifically for a MicroBlaze™ embeddedprocessor design.
上传时间： 2013-11-11
上传用户：dgann
本次在线座谈主要介绍TI的高精度Delta-Sigma A/D转换器的原理及其应用，Delta-Sigma A/D转换器在称重仪器中，大量采用比例测量方法。
标签： Delta-Sigma 高精度 转换器
上传时间： 2013-10-17
上传用户：zhqzal1014
Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full scale. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full Scale Error): The difference between theoutput voltage (or current) with full scale input code and theideal voltage (or current) that should exist with a full scale inputcode.Gain Temperature Coefficient (Full Scale TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full scale).Can be expressed as a percentage of full scale or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full scale voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.
标签： Converters Defini DAC
上传时间： 2013-10-30
上传用户：stvnash
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
上传时间： 2013-11-12
上传用户：pans0ul
PCI ExpressTM Architecture Add-in Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
标签： Architecture ExpressTM PCI
上传时间： 2013-11-03
上传用户：gy592333
cv181l-a-20
标签： Specification_V 181 1.0 L-A
上传时间： 2013-11-14
上传用户：daijun20803
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
