Although Stellaris microcontrollers have generous internal SRAM capabilities, certain applicationsmay have data storage requirements that exceed the 8 KB limit of the Stellaris LM3S8xx seriesdevices. Since microcontrollers do not have an external parallel data-bus, serial memory optionsmust be considered. Until recently, the ubiquitous serial EEPROM/flash device was the only serialmemory solution. The major limitations of EEPROM and flash technology are slow write speed, slowerase times, and limited write/erase endurance.Recently, serial SRAM devices have become available as a solution for high-speed dataapplications. The N256S08xxHDA series of devices, from AMI Semiconductor, offer 32 K x 8 bits oflow-power data storage, a fast Serial Peripheral Interface (SPI) serial bus, and unlimited write cycles.The parts are available in 8-pin SOIC and compact TSSOP packages.
上传时间： 2013-10-14
上传用户：cxl274287265
基于单DSP的VoIP模拟电话适配器研究与实现:提出和实现了一种新颖的基于单个通用数字信号处理器(DSP)的VoIP模拟电话适配器方案。DSP的I/O和存储资源非常有限，通常适于运算密集型应用，不适宜控制密集型应用[5]。该系统高效利用单DSP的I/O和片内外存储器资源，采用μC/OS-II嵌入式实时操作系统，支持SIP和TCP-UDP/IP协议，通过LAN或者宽带接入，使普通电话机成为Internet终端，实现IP电话。该系统软硬件结构紧凑高效，运行稳定，成本低，具有广阔的应用前景。关键词：模拟电话适配器；IP电话；数字信号处理器；μC/OS-II 【Abstract】This paper presents a VoIP ATA solution based on a single digital signal processor (DSP). DSPs are suitable for arithmetic-intensiveapplication and unsuitable for control-intensive application because of the limitation of I/O and memory resources. This solution is based on a 16-bitfixed-point DSP and μC/OS-II embedded real-time operating system. It makes good use of the limited resources, supports SIP and TCP-UDP/IPprotocol. It can connect the analog telephone to Internet and realize the VoIP application. This system has a great future for its high efficiency andlow cost.【Key words】Analog telephone adapter (ATA); Voice over Internet protocol (VoIP); Digital signal processor (DSP); μC/OS-II Research and Implementation of VoIPATA Based on Single DSP
上传时间： 2013-11-20
上传用户：Wwill
Abstract: There are many things to consider when designing a power supply for a field-programmablegate array (FPGA). These include (but are not limited to) the high number of voltage rails, and thediffering requirements for both sequencing/tracking and the voltage ripple limits. This application noteexplains these and other power-supply considerations that an engineer must think through whendesigning a power supply for an FPGA.
上传时间： 2013-11-10
上传用户：iswlkje
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
上传时间： 2014-01-13
上传用户：竺羽翎2222
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
标签： CPLD
上传时间： 2013-10-22
上传用户：李哈哈哈
在现代通信系统中，电话语音的频带被限制在300 Hz～4 kHz的范围内，带来了语音可懂度和自然度的降低。为了在不增加额外成本的前提下提高语音的可懂度和自然度，进行了电话语音频带扩展的研究。提出了一种改进的基于码本映射的语音带宽扩展算法：在码本映射的过程中，使用加权系数来得到映射码本。客观测试结果表明，用此算法得到的宽带语音的谱失真度比用一般的码本映射降低至少2%。主观测试结果表明，用此算法得到的宽带语音具有更好的可懂度和自然度。 Abstract: In modern communication systems， the bandwidth of telephone speech is limited from 300Hz to 4 kHz， which reduces the intelligibility and naturalness of speech. Telephone speech bandwidth extension is researched to get wideband speech and to improve its intelligibility and naturalness， without increasing extra costs. This paper put forward an improved algorithm of speech bandwidth extension based on codebook mapping. In the process of codebook mapping， weighted coefficients were used to get mapping codebook. Objective tests show that spectral distortion of wideband speech obtained by this algorithm reduces at least 2%， comparing to conditional codebook mapping. Subjective tests show that the wideband speech obtained by this algorithm has better intelligibility and naturalness.
上传时间： 2014-12-29
上传用户：15501536189
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
上传时间： 2013-11-11
上传用户：zwei41
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
标签： CPLD
上传时间： 2014-12-05
上传用户：qazxsw
摘 : 通过使用 peer-to-peer(P2P)计算模式在 Internet 物理拓扑基础上建立一个称为 P2P 覆盖网络(P overlay network)的虚拟拓扑结构,有效地建立起一个基于 Internet 的完全分布式自组织网络路由模型 集中式自组织网络路由模型(hierarchical aggregation self-organizing network,简称 HASN).分别描述了 HASN 由模型的构建目标和体系结构,并详细分析了 HASN 采用的基于 P2P 计算模式的分布式命名 路由发现和更 算法 HASN_Scale,并在仿真实验的基础上,对 HASN 路由模型的性能进行了验证.
标签： peer-to-peer P2P Internet overlay
上传时间： 2014-01-21
上传用户：zhenyushaw
人工智能中模糊逻辑算法 FuzzyLib 2.0 is a comprehensive C++ Fuzzy Logic library for constructing fuzzy logic systems with multi-controller support. It supports all commonly used shape functions and hedges, with full support for the various types of Aggregation, Correlation, Alphacut, Composition, Defuzzification methods. The latest version of the C++ Fuzzy Logic Class Library contains all the C++ source code and comes complete with a usage example for building a multi-controllers fuzzy logic model.
标签： comprehensive constructing FuzzyLib library
上传时间： 2013-12-17
上传用户：dbs012280
