This program prints the C8051F124 die temperature out the hardware UART at 115200bps. This example uses the internal 24.5MHz oscillator multiplied by 2 using the on-chip PLL (SYSCLK = 49MHz).
标签： This temperature C8051F124 the
上传时间： 2014-01-12
上传用户：Avoid98
quick die changes for manufacturing processes
标签： manufacturing processes changes quick
上传时间： 2014-09-05
上传用户：chenjjer
quick die changes
上传时间： 2016-10-26
上传用户：windwolf2000
quick die change
上传时间： 2013-11-26
上传用户：ddddddos
Data Sheet 512Mb D-die DDR SDRAM Specification
标签： Specification D-die Sheet SDRAM
上传时间： 2013-12-09
上传用户：dongbaobao
Snunuiot are flying as far as you send them... and then they die ha ha ha
上传时间： 2017-05-17
上传用户：semi1981
dieses Verzeichnis enthaelt die VHDL-Quelltexte zur Beschreibung eines "Stack-Speichers"
标签： VHDL-Quelltexte Stack-Speichers Beschreibung Verzeichnis
上传时间： 2014-01-23
上传用户：417313137
Most circuit designers are familiar with diode dynamiccharacteristics such as charge storage, voltage dependentcapacitance and reverse recovery time. Less commonlyacknowledged and manufacturer specifi ed is diode forwardturn-on time. This parameter describes the timerequired for a diode to turn on and clamp at its forwardvoltage drop. Historically, this extremely short time, unitsof nanoseconds, has been so small that user and vendoralike have essentially ignored it. It is rarely discussed andalmost never specifi ed. Recently, switching regulator clockrate and transition time have become faster, making diodeturn-on time a critical issue. Increased clock rates aremandated to achieve smaller magnetics size; decreasedtransition times somewhat aid overall effi ciency but areprincipally needed to minimize IC heat rise. At clock speedsbeyond about 1MHz, transition time losses are the primarysource of die heating.
上传时间： 2013-10-10
上传用户：谁偷了我的麦兜
Abstract: We can apply a BiCMOS integrated circuit with only resistors and no transistors to solve adifficult design problem. The mythically perfect operational amplifier's gain and temperature coefficient aredependent on external resistor values. Maxim precision resistor arrays are manufactured together on asingle die and then automatically trimmed, to ensure close ratio matching. This guarantees that theoperational amplifier (op amp) gain and temperature coefficient are predictable and reliable, even withlarge production volumes.
上传时间： 2014-11-30
上传用户：ynzfm
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
