cycle

基于Contourlet域HMT模型的cycle Spinning去噪方法

为了提高图像去噪效果，提出了基于Contourlet域HMT模型的cycle Spinning去噪方法。首先将待去噪图像进行循环平移，使用Contourlet域HMT模型对平移后的图像进行降噪处理，然后将降噪后的图像进行循环反平移，最后将不同循环平移量下的降噪图像进行平均处理，以减少去噪后图像的失真。实验结果表明，该方法不仅可以提高降噪后图像峰值信噪比，而且可以提高降噪后图像的视觉效果。

标签： Contourlet Spinning cycle HMT

上传时间： 2014-12-23

上传用户：ddddddos
cycle slip probability of the phase unrapping algorithm

cycle slip probability of the phase unrapping algorithm

标签： probability algorithm unrapping cycle

上传时间： 2013-12-09

上传用户：wpt
IEEE软件生命周期过程管理标准 IEEE Standard for Information Technology - Software Life cycle

IEEE软件生命周期过程管理标准 IEEE Standard for Information Technology - Software Life cycle

标签： IEEE Information Technology Standard

上传时间： 2014-11-11

上传用户：xlcky
ADSP-BF535 Blackfin® Processor Multi-cycle Instructions and Latencies

ADSP-BF535 Blackfin® Processor Multi-cycle Instructions and Latencies

标签： Instructions Multi-cycle Processor Latencies

上传时间： 2013-12-20

上传用户：2467478207
show 0-F cycle by cycle in ARM7

show 0-F cycle by cycle in ARM7

标签： cycle show ARM7 by

上传时间： 2016-01-11

上传用户：yph853211
This demo shows the use of the PWM block in generating the pulse waveform whose duty cycle is changi

This demo shows the use of the PWM block in generating the pulse waveform whose duty cycle is changing regularly. The PWM waveform period is variable, while the width of the pulse remains constant.

标签： the generating waveform changi

上传时间： 2014-01-15

上传用户：kr770906
VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..

VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..

标签： with resulting waveform circuit

上传时间： 2014-01-05

上传用户：woshini123456
CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 b

CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset

标签： polynomial Features Executes clock

上传时间： 2013-12-18

上传用户：Ants
Ring register[1 from 8] which seven speeds. The result is presented on 8 LEDs. After every cycle, sp

Ring register[1 from 8] which seven speeds. The result is presented on 8 LEDs. After every cycle, speed grows. The process starts again after last 8 cycle.

标签： presented register result speeds

上传时间： 2017-03-24

上传用户：llandlu
Write a program to decide if a graph has a cycle or not. The given graph can be a directed or undire

Write a program to decide if a graph has a cycle or not. The given graph can be a directed or undirected graph, which is indicated at the time of reading the input (0 for directed graph and 1 for undirected graphs). The input is given as an adjacency list.

标签： graph directed program decide

上传时间： 2013-12-23

上传用户：cursor

cycle

基于Contourlet域HMT模型的cycle Spinning去噪方法

cycle slip probability of the phase unrapping algorithm

IEEE软件生命周期过程管理标准 IEEE Standard for Information Technology - Software Life cycle

ADSP-BF535 Blackfin® Processor Multi-cycle Instructions and Latencies

show 0-F cycle by cycle in ARM7

This demo shows the use of the PWM block in generating the pulse waveform whose duty cycle is changi

VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..

CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 b

Ring register[1 from 8] which seven speeds. The result is presented on 8 LEDs. After every cycle, sp

Write a program to decide if a graph has a cycle or not. The given graph can be a directed or undire