UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
上传时间： 2013-11-02
上传用户：18862121743
ADS2012成功破解详细步骤
上传时间： 2013-11-06
上传用户：gououo
FANUC 31I PMC密码破解程序
上传时间： 2015-01-02
上传用户：cccole0605
4层楼电梯程序，请大家多多指教。
上传时间： 2015-01-02
上传用户：xja31415
PLC（可编程序控制器）原理和基础知识4
上传时间： 2013-10-26
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Multisim_11.0详细的_安装 汉化 破解_全过程
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LabVIEW最简单的破解方法_包括2011版的
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上传用户：dajin
特点 精确度0.05%滿刻度 ±1位數 可量测交直流電流/交直流电压/電位計/傳送器/Pt-100/荷重元/電阻等信号 显示范围0- ±19999可任意规划 数位化指拨设定操作简易 具有自动归零与保持功能 4组警报功能 15BIT 类比输出功能 数位RS-485界面
上传时间： 2013-10-18
上传用户：dianxin61
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上传时间： 2013-12-25
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4位共阳LED数码管引脚连接
上传时间： 2013-11-05
上传用户：ljmwh2000
