#include<stdio.h> #define TREEMAX 100 typedef struct BT { char data; BT *lchild; BT *rchild; }BT; BT *CreateTree(); void Preorder(BT *T); void Postorder(BT *T); void Inorder(BT *T); void Leafnum(BT *T); void Nodenum(BT *T); int TreeDepth(BT *T); int count=0; void main() { BT *T=NULL; char ch1,ch2,a; ch1='y'; while(ch1=='y'||ch1=='y') { printf("\n"); printf("\n\t\t 二叉树子系统"); printf("\n\t\t*****************************************"); printf("\n\t\t 1---------建二叉树 "); printf("\n\t\t 2---------先序遍历 "); printf("\n\t\t 3---------中序遍历 "); printf("\n\t\t 4---------后序遍历 "); printf("\n\t\t 5---------求叶子数 "); printf("\n\t\t 6---------求结点数 "); printf("\n\t\t 7---------求树深度 "); printf("\n\t\t 0---------返 回 "); printf("\n\t\t*****************************************"); printf("\n\t\t 请选择菜单号 （0--7）"); scanf("%c",&ch2); getchar(); printf("\n"); switch(ch2) { case'1': printf("\n\t\t请按先序序列输入二叉树的结点:\n"); printf("\n\t\t说明：输入结点（‘0’代表后继结点为空）后按回车。\n"); printf("\n\t\t请输入根结点:"); T=CreateTree(); printf("\n\t\t二叉树成功建立！\n");break; case'2': printf("\n\t\t该二叉树的先序遍历序列为:"); Preorder(T);break; case'3': printf("\n\t\t该二叉树的中序遍历序列为:"); Inorder(T);break; case'4': printf("\n\t\t该二叉树的后序遍历序列为:"); Postorder(T);break; case'5': count=0;Leafnum(T); printf("\n\t\t该二叉树有%d个叶子。\n",count);break; case'6': count=0;Nodenum(T); printf("\n\t\t该二叉树总共有%d个结点。\n",count);break; case'7': printf("\n\t\t该树的深度为:%d",TreeDepth(T)); break; case'0': ch1='n';break; default: printf("\n\t\t***请注意：输入有误！***"); } if(ch2!='0') { printf("\n\n\t\t按【Enter】键继续，按任意键返回主菜单！\n"); a=getchar(); if(a!='\xA') { getchar(); ch1='n'; } } } } BT *CreateTree() { BT *t; char x; scanf("%c",&x); getchar(); if(x=='0') t=NULL; else { t=new BT; t->data=x; printf("\n\t\t请输入%c结点的左子结点:",t->data); t->lchild=CreateTree(); printf("\n\t\t请输入%c结点的右子结点:",t->data); t->rchild=CreateTree(); } return t; } void Preorder(BT *T) { if(T) { printf("%3c",T->data); Preorder(T->lchild); Preorder(T->rchild); } } void Inorder(BT *T) { if(T) { Inorder(T->lchild); printf("%3c",T->data); Inorder(T->rchild); } } void Postorder(BT *T) { if(T) { Postorder(T->lchild); Postorder(T->rchild); printf("%3c",T->data); } } void Leafnum(BT *T) { if(T) { if(T->lchild==NULL&&T->rchild==NULL) count++; Leafnum(T->lchild); Leafnum(T->rchild); } } void Nodenum(BT *T) { if(T) { count++; Nodenum(T->lchild); Nodenum(T->rchild); } } int TreeDepth(BT *T) { int ldep,rdep; if(T==NULL) return 0; else { ldep=TreeDepth(T->lchild); rdep=TreeDepth(T->rchild); if(ldep>rdep) return ldep+1; else return rdep+1; } }
上传时间： 2020-06-11
上传用户：ccccy
#include <stdio.h> #include <stdlib.h> #define SMAX 100 typedef struct SPNode { int i,j,v; }SPNode; struct sparmatrix { int rows,cols,terms; SPNode data [SMAX]; }; sparmatrix CreateSparmatrix() { sparmatrix A; printf("\n\t\t请输入稀疏矩阵的行数，列数和非零元素个数（用逗号隔开）:"); scanf("%d,%d,%d",&A.cols,&A.terms); for(int n=0;n<=A.terms-1;n++) { printf("\n\t\t输入非零元素值（格式：行号，列号，值）:"); scanf("%d,%d,%d",&A.data[n].i,&A.data[n].j,&A.data[n].v); } return A; } void ShowSparmatrix(sparmatrix A) { int k; printf("\n\t\t"); for(int x=0;x<=A.rows-1;x++) { for(int y=0;y<=A.cols-1;y++) { k=0; for(int n=0;n<=A.terms-1;n++) { if((A.data[n].i-1==x)&&(A.data[n].j-1==y)) { printf("%8d",A.data[n].v); k=1; } } if(k==0) printf("%8d",k); } printf("\n\t\t"); } } void sumsparmatrix(sparmatrix A) { SPNode *p; p=(SPNode*)malloc(sizeof(SPNode)); p->v=0; int k; k=0; printf("\n\t\t"); for(int x=0;x<=A.rows-1;x++) { for(int y=0;y<=A.cols-1;y++) { for(int n=0;n<=A.terms;n++) { if((A.data[n].i==x)&&(A.data[n].j==y)&&(x==y)) { p->v=p->v+A.data[n].v; k=1; } } } printf("\n\t\t"); } if(k==1) printf("\n\t\t对角线元素的和：:%d\n",p->v); else printf("\n\t\t对角线元素的和为：:0"); } int main() { int ch=1,choice; struct sparmatrix A; A.terms=0; while(ch) { printf("\n"); printf("\n\t\t 稀疏矩阵的三元组系统 "); printf("\n\t\t*********************************"); printf("\n\t\t 1------------创建 "); printf("\n\t\t 2------------显示 "); printf("\n\t\t 3------------求对角线元素和"); printf("\n\t\t 4------------返回 "); printf("\n\t\t*********************************"); printf("\n\t\t请选择菜单号（0-3）:"); scanf("%d",&choice); switch(choice) { case 1: A=CreateSparmatrix(); break; case 2: ShowSparmatrix(A); break; case 3: SumSparmatrix(A); break; default: system("cls"); printf("\n\t\t输入错误！请重新输入！\n"); break; } if (choice==1||choice==2||choice==3) { printf("\n\t\t"); system("pause"); system("cls"); } else system("cls"); } }
上传时间： 2020-06-11
上传用户：ccccy
Research on microwave power amplififiers has gained a growing importance demanded by the many continuously developing applications which require such subsystem performance. A broad set of commercial and strategic systems in fact have their overall performance boosted by the power amplififier, the latter becoming an enabling component wherever its effificiency and output power actually allows functionalities and operating modes previously not possible. This is the case for the many wireless systems and battery-operated systems that form the substrate of everyday life, but also of high-performance satellite and dual-use systems.
上传时间： 2021-10-30
上传用户：得之我幸78
MAX30102芯片心率血氧传感器模块传感器模块软硬件设计资料包括STM32测试源码AD设计原理图及心率及血氧参考设计资料:参考代码及实验数据工程文件及库心率及血氧参考设计资料芯片数据手册1771.pdf2ES Teck PEMS White Paper.pdf31930_accessories.pdf5273c08fe2b6b_1_4264142A_EN_p.pdfAvant 2120 Brochure.pdfcelyon-1057-daeg.pdfDr. Bob case study for dental.pdfenvitec.pdfgclarke-2015-MASc-thesis.pdfiadt02i4p261.pdfIHE_PCD_Suppl_POI.pdfijcsit2014050679.pdfIMECS2009_pp1537-1540.pdfLuksSwensonPulseOximetryatHighAltitude.pdfMI_CCHD_Screener_Tips_Flier_3-21-13_422078_7.pdfMoon.pdfnotes6.pdfpansw_spo2_sensor.pdfPK_EN_MAsimo2008Product Catalog.pdfpm-60a-spo2-report-4.pdfpulse-oximetry-at-home.pdfpulse-oximetry.pdfpulse.pdfPulseOxFinal_low.pdfpulse_ox.pdfpxc3976461.pdfReusable SpO2 Sensors.pdfSP02-cross-reference-sensor.pdfsprt533.pdfsszb140.pdfview.pdf
上传时间： 2021-11-24
上传用户：fliang
常用芯片表贴芯片表贴电阻电容STM封装库AD库（ATIUM PCB封装库）:PCB Library : 常用芯片表贴芯片表贴电阻电容STM封装库AD库（ATIUM PCB封装库）.PcbLibDate : 2021/5/14Time : 16:14:01Component Count : 463Component Name-----------------------------------------------LC-12-DIPH-300LC-0201LC-0201_CLC-0201_LLC-0201_RLC-0402LC-0402_CLC-0402_LLC-0402_RLC-0402_Rx2LC-0402_Rx4LC-0603LC-0603_CLC-0603_Cx4LC-0603_LLC-0603_LEDLC-0603_RLC-0603_Rx2LC-0603_Rx4LC-0805LC-0805_CLC-0805_LLC-0805_LEDLC-0805_RLC-1206LC-1206_CLC-1206_LLC-1206_RLC-1210LC-1210_CLC-1210_RLC-1806LC-1806_CLC-1806_LLC-1806_RLC-1808LC-1808_CLC-1808_LLC-1808_RLC-1812LC-1812_CLC-1812_LLC-1812_RLC-1825LC-1825_CLC-1825_LLC-1825_RLC-2010LC-2010_CLC-2010_LLC-2010_RLC-2220LC-2220_CLC-2220_LLC-2220_RLC-2225LC-2225_CLC-2225_RLC-2512LC-2512_CLC-2512_LLC-2512_RLC-ABSLC-BGA-14LC-BGA-84_7.5x12.5mmLC-BGA-121LC-BGA-143LC-BR-3LC-BR-6LC-BR-10LC-case 017AA-01LC-case-A_3216LC-case-B_3528LC-case-C_6032LC-case-D_7343LC-case-E_7343LC-case-P_2012LC-case-R_2012LC-DBLC-DBSLC-DFN-2LLC-DFN-8_3x3mmLC-DFN-8_5x6mmLC-DFN-10_3x3mmLC-DFN-10_EP_3x3mmLC-DIP-4LC-DIP-5LC-DIP-6LC-DIP-7LC-DIP-8LC-DIP-14LC-DIP-16LC-DIP-18LC-DIP-20LC-DIP-24_300milLC-DIP-24_600milLC-DIP-28_300milLC-DIP-28_600milLC-DIP-40LC-DO-15LC-DO-27LC-DO-35LC-DO-41LC-DO-201ADLC-DO-213AALC-DO-213ABLC-DO-218ABLC-DSON-10LC-FBGA-84_9x12.5mmLC-FBGA-96_8x14mmLC-FBGA-256LC-FBGA-272LC-FBGA-289LC-FBGA-484LC-FBGA-780LC-GBJLC-GBULC-GDTs_SMDLC-GDTs_THTLC-HC-49SLC-HC-49SMDLC-HC-49ULC-HTSSOP-32LC-HVMDIPLC-HVQFN-32_5x5x05PLC-HZIP25-P-1.27LC-KBJLC-KBLLC-KBPLC-KBPCLC-KBULC-LBSLC-LFBGA-217LC-LFCSP-8_3x2x05PLC-LFCSP-8_3x3x05PLC-LFCSP-16_4x4x05PLC-LFCSP-20_4x4x05PLC-LFCSP-24_4x4x05PLC-LFCSP-28_5x5x05PLC-LFCSP40_6x6x05PLC-LFCSP56_8x8x05PLC-LGA-8_3x5mmLC-LGA-14_3x5mmLC-LGA-16_3x3mmLC-LGA-16_4x4mmLC-LL-34LC-LL-35LC-LL-41LC-LPCC-148LC-LQFP-32_7x7x08PLC-LQFP-44_10x10x08PLC-LQFP-48_7x7x05P
上传时间： 2021-12-02
上传用户：
FPGA片内FIFO读写测试Verilog逻辑源码Quartus工程文件+文档说明，使用 FPGA 内部的 FIFO 以及程序对该 FIFO 的数据读写操作。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz时钟 input rst_n //复位信号，低电平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO写数据wire wr_en; //FIFO写使能wire rd_en; //FIFO读使能wire[15:0] r_data; //FIFO读数据wire full; //FIFO满信号 wire empty; //FIFO空信号 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///产生FIFO写入的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空， 开始写FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO满 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///产生FIFO读的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO满, 开始读FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)
上传时间： 2021-12-19
上传用户：20125101110
电子书-RTL Design Style Guide for Verilog HDL540页A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
标签： RTL verilog hdl
上传时间： 2022-03-21
上传用户：canderile
设计了自动控制系统综合实验案例“基于LabVIEW和单片机的温度控制系统设计”。实验系统硬件部分由单片机、温度传感器、D/A转换模块、调压模块和电烤箱组成,设计了单片机与各个模块之间的接口电路。软件部分采用LabVIEW软件实现控制算法,并设计监控界面实现参数设定、温度数据实时监控等功能。设计了单片机与LabVIEW软件之间的串口通信程序,实现了输入、输出数据的传输。通过综合实验系统设计,使学生得到控制系统设计和实验调试等综合能力的训练。A comprehensive experimental case of the automatic control system is presented,which is the design of the temperature control system based on LabVIEW and SCM.The hardware part of the experimental system is composed of the SCM,temperature sensor,D/A conversion module,voltage regulating module and electric oven.The interface circuit between the SCM and each module is designed.In the software part,LabVIEW software is used to realize the control algorithm,and the monitoring interface is designed to realize the functions of parameter setting,temperature data real-time monitoring,etc.The serial communication program between the SCM and LabVIEW software is designed to realize the transmission of input and output data.Through the design of this comprehensive experimental system,students can get the comprehensive ability training for the control system design,experiment debugging,etc.
上传时间： 2022-03-27
上传用户：qdxqdxqdxqdx
为了提高超高频RFID系统中阅读器在低信噪比的情况下仍具有较高的识别能力,提出一种基于FPGA系统结合软件无线电方法实现超高频RFID射频前端电路方案。超高频射频识别系统必须符合EPC Class 1generation 2标准,所设计的电路系统以Xilinx公司的XC6SLX16-2CSG324FPGA芯片为硬件基础,将数字基带调制解调和中频滤波电路在FPGA系统中设计实现,重点阐述了射频前端电路的设计结构、AD/DA转换电路,以及数字滤波器的设计。实验结果表明,所设计的超高频RFID阅读器简化了前端电路系统结构,提升了稳定性,增强了抗干扰能力。该电路系统在信噪比较低的情况下,能够较好地实现915MHz频率的射频接收和发送。In order to improve the reader UHF RFID system still has a higher ability to identify,in the case of low signal-to-noise ratio.The UHF RFID systems must comply with EPC Class 1 generation 2 standard.In this paper,the design of the circuit system based on Xilinx＇s XC6SLX16-2CSG324 FPGA chip,and presents UHF RFID RF front-end circuit with software radio based on FPGA system.Digital baseband modem and IF filter circuit is designed and implemented in the FPGA system,and focused on designing the structure of the RF front-end circuit,AD/DA conversion circuits,and digital filter.Experimental results show that the UHF RFID reader de...
标签： 915mhz 超高频 rfid 阅读 射频 前端 电路 设计
上传时间： 2022-04-17
上传用户：shjgzh
#include "NUC1xx.h"#include "Hal.h"#include "pwm.h"//wait current PWM cycle done, otherwise there maybe short pulse on FETvoid PWM_Stop(U8 ch){ switch(ch) { case PWM_CHANNEL_A: PWMA->u32CNR1 = 0; PWMA->u32CMR1 = 0; while(PWMA->u32PDR1 != 0); break; case PWM_CHANNEL_B: PWMA->u32CNR2 = 0; PWMA->u32CMR2 = 0; while(PWMA->u32PDR2 != 0); break; case PWM_CHANNEL_C: PWMA->u32CNR3 = 0; PWMA->u32CMR3 = 0; while(PWMA->u32PDR3 != 0); break; default: while(1); } PWMA->u32POE &= ~(1<<ch); PWMA->u32PCR &= ~(1<<(ch*8));}
上传时间： 2022-06-01
上传用户：kingwide
