This paper examines the asymptotic (large sample) performance of a family of non-data aided feedforward (NDA FF) nonlinear least-squares (NLS) type carrier frequency estimators for burst-mode phase shift keying (PSK) modulations transmitted through AWGN and flat Ricean-fading channels. The asymptotic performance of these estimators is established in closed-form expression and compared with the modified Cram`er-Rao bound (MCRB). A best linear unbiased estimator (BLUE), which exhibits the lowest asymptotic variance within the family of NDA FF NLS-type estimators, is also proposed.
标签： performance asymptotic examines non-data
上传时间： 2015-12-30
上传用户：225588
S29NS-J 128 Megabit (8 M x 16-Bit), 64 Megabit (4 M x 16-Bit), 32 Megabit (2 M x 16-Bit), and 16 Megabit (1 M x 16 Bit), 110 nm CMOS 1.8-Volt only Simultaneous Read/Write, burst Mode Flash Memories Data Sheet
上传时间： 2014-01-01
上传用户：qoovoop
自相似、长相关业务的生成及TCP拥塞控制的研究 目前,Internet的规模日益增大,承载的业务种类也不断增加.Internet已给人们的生活和工作带来了巨大的利益和影响.21世纪是通信的世纪,是互连网的世纪.经过20多年的发展,Internet已经在全球取得巨大的成功.该文对自相似、长相关基本理论进行了研究,得出了生成自相似、长相关业务的方法,即通过重尾分布ON/OFF源的N-burst模型的聚合业务来生成自相似、长相关业务,使用国际上比较通用的仿真软件NS-2来进行仿真.并基于此特征业务,对TCP性能进行分析.最后对TCP拥塞控制进行改进,以适合自相似、长相关的的网络特性,提高网络性能.
上传时间： 2013-12-18
上传用户：yxgi5
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
标签： Tensilica OpenCores interface the
上传时间： 2013-12-21
上传用户：gonuiln
#define RF_CHANNEL 25 // 2.4 GHz RF channel // BasicRF address definitions µØÖ·¶¨Òå #define PAN_ID 0x2007 #define TX_ADDR 0xBEEF #define RX_ADDR 0x2520 // transmit data ´«ÊäÊý¾Ý #define APP_PAYLOAD_LENGTH 1 //Ó¦ÓóÌÐò¸ºÔس¤¶È #define MAX_PAYLOAD_LENGTH 104 #define PACKET_SIZE sizeof(perTestPacket_t) #define RSSI_AVG_WINDOW_SIZE 32 // Window size for RSSI moving average // burst Sizes #define burst_SIZE_1 1000 #define burst_SIZE_2 10000 #define burst_SIZE_3 100000 #define burst_SIZE_4 1000000
上传时间： 2017-02-28
上传用户：DoubleM
There is a phenomenal burst of research activities in mobile cloud computing systems, which extends cloud computing functions, ser- vices, and results to the world of future mobile communications applications, and the paradigm of cloud computing and virtualization to mobile networks. Mobile applications demand greater resources and improved interactivity for better user experience.
标签： Mobile Cloud Computing Systems
上传时间： 2020-05-30
上传用户：shancjb
基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter burst_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
标签： fpga sdram verilog quartus
上传时间： 2021-12-18
上传用户：
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
标签： DDR4
上传时间： 2022-01-09
上传用户：
