The LTC®1966 is a true RMS-to-DC converter that uses aDS computational technique to make it dramatically simplerto use, significantly more accurate, lower in powerconsumption and more flexible than conventional logantilogRMS-to-DC converters. The LTC1966 RMS-to-DCconverter has an input signal range from 5mVRMS to1.5VRMS (a 50dB dynamic range with a single 5V supplyrail) and a 3dB bANDwidth of 800kHz with signal crestfactors up to four.
上传时间： 2013-10-12
上传用户：qilin
Abstract: Transimpedance amplifiers (TIAs) are widely used to translate the current output of sensors like photodiode-to-voltagesignals, since several circuits and instruments can only accept voltage input. An operational amplifier with a feedback resistor fromoutput to the inverting input is the most straightforward implementation of such a TIA. However, even this simple TIA circuit requirescareful trade-offs among noise gain, offset voltage, bANDwidth, and stability. Clearly stability in a TIA is essential for good, reliableperformance. This application note explains the empirical calculations for assessing stability and then shows how to fine-tune theselection of the feedback phase-compensation capacitor.
标签： Transimpedance Stabilize Amplifier Your
上传时间： 2013-11-13
上传用户：daoyue
Recent advances in low voltage silicon germaniumand BiCMOS processes have allowed the design andproduction of very high speed amplifi ers. Because theprocesses are low voltage, most of the amplifi er designshave incorporated differential inputs and outputs to regainand maximize total output signal swing. Since many lowvoltageapplications are single-ended, the questions arise,“How can I use a differential I/O amplifi er in a single-endedapplication?” and “What are the implications of suchuse?” This Design Note addresses some of the practicalimplications and demonstrates specifi c single-endedapplications using the 3GHz gain-bANDwidth LTC6406differential I/O amplifi er.
上传时间： 2013-11-23
上传用户：rocketrevenge
Highlights the LTC1062 as a lowpass filter in a phase lock loop. Describes how the loop's bANDwidth can be increased and the VCO output jitter reduced when the LTC1062 is the loop filter. Compares it with a passive RC loop filter. Also discussed is the use of LTC1062 as simple bandpass and bandstop filter.
上传时间： 2013-10-24
上传用户：chens000
ANALOG INPUT bANDwidth is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbANDwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
上传时间： 2013-11-12
上传用户：pans0ul
In this paper, two types of MMIC voltage controlled oscillators have been successfully demonstrated. The first chip with single tuning diode shows the excellent tuning linearity. The second chip with two tuning diodes can improve the tuning bANDwidth.
上传时间： 2013-10-17
上传用户：xjz632
高的工作电压高达100V N双N沟道MOSFET同步驱动 The D810DCDC is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 100V, making it ideal for telecom and automotive applications. The D810DCDC uses a constant on-time valley current control architecture to deliver very low duty cycles with accurate cycle-by-cycle current limit, without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bANDwidth (25MHz) error amplifi er provides very fast line and load transient response. Large 1Ω gate drivers allow the D810DCDC to drive multiple MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN and can also be synchronized to an external clock for switching-noise sensitive applications. Integrated bias control generates gate drive power from the input supply during start-up and when an output shortcircuit occurs, with the addition of a small external SOT23 MOSFET. When in regulation, power is derived from the output for higher effi ciency.
上传时间： 2013-10-24
上传用户：wd450412225
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bANDwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上传时间： 2013-10-08
上传用户：18711024007
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bANDwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
This application note describes how the existing dual-port block memories in the Spartan™-IIand Virtex™ families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bANDwidth of the blockmemory in terms of bits per second will remain the same.
上传时间： 2013-11-08
上传用户：lou45566
