Hyperlynx仿真应用:阻抗匹配.下面以一个电路设计为例,简单介绍一下PCB仿真软件在设计中的使用。下面是一个DSP硬件电路部分元件位置关系(原理图和PCB使用PROTEL99SE设计),其中DRAM作为DSP的扩展Memory(64位宽度,低8bit还经过3245接到FLASH和其它芯片),DRAM时钟频率133M。因为频率较高,设计过程中我们需要考虑DRAM的数据、地址和控制线是否需加串阻。下面,我们以数据线D0仿真为例看是否需要加串阻。模型建立首先需要在元件公司网站下载各器件IBIS模型。然后打开Hyperlynx,新建LineSim File(线路仿真—主要用于PCB前仿真验证)新建好的线路仿真文件里可以看到一些虚线勾出的传输线、芯片脚、始端串阻和上下拉终端匹配电阻等。下面,我们开始导入主芯片DSP的数据线D0脚模型。左键点芯片管脚处的标志,出现未知管脚,然后再按下图的红线所示线路选取芯片IBIS模型中的对应管脚。 3http://bbs.elecfans.com/ 电子技术论坛 http://www.elecfans.com 电子发烧友点OK后退到“assign Models”界面。选管脚为“Output”类型。这样,一样管脚的配置就完成了。同样将DRAM的数据线对应管脚和3245的对应管脚IBIS模型加上(DSP输出,3245高阻,DRAM输入)。下面我们开始建立传输线模型。左键点DSP芯片脚相连的传输线,增添传输线,然后右键编辑属性。因为我们使用四层板,在表层走线,所以要选用“Microstrip”,然后点“Value”进行属性编辑。这里,我们要编辑一些PCB的属性,布线长度、宽度和层间距等,属性编辑界面如下:再将其它传输线也添加上。这就是没有加阻抗匹配的仿真模型(PCB最远直线间距1.4inch,对线长为1.7inch)。现在模型就建立好了。仿真及分析下面我们就要为各点加示波器探头了,按照下图红线所示路径为各测试点增加探头:为发现更多的信息,我们使用眼图观察。因为时钟是133M,数据单沿采样,数据翻转最高频率为66.7M,对应位宽为7.58ns。所以设置参数如下:之后按照芯片手册制作眼图模板。因为我们最关心的是接收端(DRAM)信号,所以模板也按照DRAM芯片HY57V283220手册的输入需求设计。芯片手册中要求输入高电平VIH高于2.0V,输入低电平VIL低于0.8V。DRAM芯片的一个NOTE里指出,芯片可以承受最高5.6V,最低-2.0V信号(不长于3ns):按下边红线路径配置眼图模板:低8位数据线没有串阻可以满足设计要求,而其他的56位都是一对一,经过仿真没有串阻也能通过。于是数据线不加串阻可以满足设计要求,但有一点需注意,就是写数据时因为存在回冲,DRAM接收高电平在位中间会回冲到2V。因此会导致电平判决裕量较小,抗干扰能力差一些,如果调试过程中发现写RAM会出错,还需要改版加串阻。
上传时间: 2013-12-17
上传用户:debuchangshi
Explain how to open the Waveform Viewer for Verification ? State how to insert nodes into the Waveform Viewer ? Tell how to assign Stimulus with the Stimulator Selector
标签: Foundation 仿真
上传时间: 2013-10-29
上传用户:daguogai
It may analyze the window structure, the advancement and the window news, has the very greatly auxiliary function to the development work. When we need to study some object, so long as assigns out its search window, drives the detector the indicator to assign the window/to control on to release then. Under, the author on and everybody same place, makes with VC to belong to own Spy++.
标签: the window advancement structure
上传时间: 2013-12-31
上传用户:ghostparker
How the K-mean Cluster work Step 1. Begin with a decision the value of k = number of clusters Step 2. Put any initial partition that classifies the data into k clusters. You may assign the training samples randomly, or systematically as the following: Take the first k training sample as single-element clusters assign each of the remaining (N-k) training sample to the cluster with the nearest centroid. After each assignment, recomputed the centroid of the gaining cluster. Step 3 . Take each sample in sequence and compute its distance from the centroid of each of the clusters. If a sample is not currently in the cluster with the closest centroid, switch this sample to that cluster and update the centroid of the cluster gaining the new sample and the cluster losing the sample. Step 4 . Repeat step 3 until convergence is achieved, that is until a pass through the training sample causes no new assignments.
标签: the decision clusters Cluster
上传时间: 2013-12-21
上传用户:gxmm
表达式类型的实现: 1、 一个表达式和一颗二叉树之间,存在着自然的对应关系。 2、 假设算术表达式Expression内可以含有变量(a~z)、常量(0~9)和二元运算符(+,-,*,/,^)。实现一下操作。 (1) ReadExpr(E)——以字符序列的形式输入语法正确的前缀表示式并构造表达式E。 (2) WritrExpr(E)——用带括弧的中缀表示式输出表达式E。 (3) assign(V,c)——实现对变量V的赋值(V=c),变量的初值为0。 (4) Value(E)——对算术表达式E求值。 (5) CompoundExpr(P,E1,E2)——构造一个新的复合表达式(E1)P (E2)。
上传时间: 2013-12-09
上传用户:luke5347
1.一个表达式和一个二叉树之间,存在着自然的对应关系。写一个程序,实现基于二叉树表示的算术表达式Expression的操作。 2.假设算术表达式Expression内可以含有变量(a~z)、常量(0~9)和二元运算符(+,-,*,/,^(乘幂))。实现以下操作: ⑴ReadExpr(E)——以字符序列的形式输入语法正确的前缀表达式并构造表达式E。 ⑵WriteExpr(E)——用带括弧的中缀表达式输出表达式E。 ⑶assign(V,c)——实现对变量Vde赋值(V=c),变量的初值为0。 ⑷Value(E)——对算术表达式E求值。 ⑸CompoundExpr(P,E1,E2)——构造一个新的复合表达式(E1)P(E2)。 3.在读入表达的字符序列的同时,完成运算符和运算数的识别和处理以及相应的运算。 4.在识别出运算数的同时,要将其字符形式转换成整数形式。 5.用在后根遍历的次序对表达式求值。
上传时间: 2014-11-27
上传用户:偷心的海盗
夏宇闻8位RISC_CPU的完整代码+TESTBENCH(已调试) modelsim工程文件,包括书中所测试的三个程序和相关数据,绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的,只有一个mcu的代码,但很多和书中的是不一样的,自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方,如clk_gen.v中clk2,clk4是没有用的,assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的,会使时序恶化,综合时很可能会setup vio的,所以觉得直接用clk的上升沿来触发各个module比较好
标签: TESTBENCH RISC_CPU modelsim 8位
上传时间: 2014-01-08
上传用户:ippler8
Airline Reservations System A small airline has just purchased a computer for its new automated reservation system. You have been asked to develop the new system called ARSystem. You are to write an application to assign seats on each flight of the airline s only plane (capacity: 24 seats.) Your application should display the following alternatives: Please type 1 for FirstClass and Please type 2 for Economy. If the user types 1, your application should assign a seat in the first-class section (seats 1-8). If the user types 2, your application should assign a seat in the economy section (seats 9-24). Your application should then display a boarding pass indicating the person s seat number and whether it is in the first-class or economy
标签: Reservations automated purchased computer
上传时间: 2017-04-14
上传用户:lizhizheng88
In this paper we present a classifier called bi-density twin support vector machines (BDTWSVMs) for data classification. In the training stage, BDTWSVMs first compute the relative density degrees for all training points using the intra-class graph whose weights are determined by a local scaling heuristic strategy, then optimize a pair of nonparallel hyperplanes through two smaller sized support vector machine (SVM)-typed problems. In the prediction stage, BDTWSVMs assign to the class label depending on the kernel density degree-based distances from each test point to the two hyperplanes. BDTWSVMs not only inherit good properties from twin support vector machines (TWSVMs) but also give good description for data points. The experimental results on toy as well as publicly available datasets indicate that BDTWSVMs compare favorably with classical SVMs and TWSVMs in terms of generalization
标签: recognition Bi-density machines support pattern vector twin for
上传时间: 2019-06-09
上传用户:lyaiqing
基于FPGA设计的字符VGA LCD显示实验Verilog逻辑源码Quartus工程文件+文档说明,通过字符转换工具将字符转换为 8 进制 mif 文件存放到单端口的 ROM IP 核中,再从ROM 中把转换后的数据读取出来显示到 VGA 上,FPGA型号Cyclone4E系列中的EP4CE6F17C8,Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上传时间: 2021-12-18
上传用户: