This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
The LTP5900 includes sufficient power supply filtering and decoupling capacitancesuch that additional filtering should not be necessary for most battery-powereddesigns. Care must be taken to avoid large transient voltages on the supply as theM2510 steps up its current consumption (see the section on Supply Design below).
标签： Integration Hardware Guide 5900
上传时间： 2014-12-24
上传用户：youmo81
Video cable driver amplifi er output stages traditionallyrequire a supply voltage of at least 6V in order to providethe required output swing. This requirement is usuallymet with 5V supplies by adding a boost regulator or asmall local negative rail, say via the popular LT®1983-3.Such additional circuitry is unnecessary in typical 1VP-Pvideo connections, such as HD component video, if thecable driver amplifi ers simply offer near rail-to-rail outputcapability when powered from 5V.
上传时间： 2013-11-16
上传用户：yanyangtian
Many system designers need an easy way to producea negative 3.3V power supply. In systems that alreadyhave a transformer, one option is to swap out the existingtransformer with one that has an additional secondarywinding. The problem with this solution is that manysystems now use transformers that are standard, offthe-shelf components, and most designers want toavoid replacing a standard, qualifi ed transformer with acustom version. An easier alternative is to produce thelow negative voltage rail by stepping down an existingnegative rail. For example, if the system already employsan off-the-shelf transformer with two secondary windingsto produce ±12V, and a –3.3V rail is needed, a negativebuck converter can produce the –3.3V output from the–12V rail.
上传时间： 2013-10-09
上传用户：Jerry_Chow
Designing read/write device (RWD) units for industrial RF-Identification applications is strongly facilitated by the NXP Semiconductors HITAG Reader Chip HTRC110. All needed function blocks, like the antenna driver, modulator demodulator and antenna diagnosis unit, are integrated in the HTRC110. Therefore only a minimum number of additional passive components are required for a complete RWD. This Application Note describes how to design an industrial RF-Identification system with the HTRC110. The major focus is dimensioning of the antenna, all other external components including clock and power supply, as well as the demodulation principle and its implementatio
上传时间： 2013-10-22
上传用户：zhengjian
The PCA9536 is an 8-pin CMOS device that provides 4 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
上传时间： 2013-10-27
上传用户：w230825hy
The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
上传时间： 2013-11-17
上传用户：vodssv
The CAT28LV64 is a low voltage, low power, CMOS Parallel EEPROM organized as 8K x 8−bits. It requires a simple interface for in−system programming. On−chip address and data latches, self−timed write cycle with auto−clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bit signal the start and end of the self−timed write cycle. additionally, the CAT28LV64 features hardware and software write protection.
上传时间： 2013-11-16
上传用户：浩子GG
The HCS12X family is the successor to the HCS12family, with many additional features. One new feature isthe increased memory available to the CPU and themethods available to access it. This document focuses onthe improved memory map configuration.
上传时间： 2013-11-13
上传用户：王者A
The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
上传时间： 2013-10-10
上传用户：inwins
