C++在几乎所有的计算环境中都非常普及，而且可以用于几乎所有的应用程序。C++从C中继承了过程化编程的高效性，并集成了面向对象编程的功能。C++在其标准库中提供了大量的功能。有许多商业C++库支持数量众多的操作系统环境和专业应用程序。但因为它的内容太多了，所以掌握C++并不十分容易。本书详述了C++语言的各个方面，包括数据类型、程序控制、函数、指针、调试、类、重载、继承、多态性、模板、异常和输入输出等内容。每一章都以前述内容为基础，每个关键点都用具体的示例进行详细的讲解。本书基本不需要读者具备任何C++知识，书中包含了理解C++的所有必要知识，读者可以从头开始编写自己的C++程序。本书也适合于具备另一种语言编程经验但希望全面掌握C++语言的读者。 I created all the files under Microsoft Windows so lines are terminated by CR/LF. In additiOn to this "ReadMe" file you will find three zip archives in the primary archive, so you need to unzip each of these to get at the code. 为PDG格式,这有pdg阅读器下载|pdg文件阅读器下载
标签： 源代码
上传时间： 2013-11-18
上传用户：gaoqinwu
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in additiOn to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-21
上传用户：wxqman
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In additiOn, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 图Figure 1. Local Safety System
上传时间： 2013-11-14
上传用户：zoudejile
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In additiOn, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
标签： PicoBlaze Create Master Xilinx
上传时间： 2013-11-12
上传用户：大三三
解压密码：www.elecfans.com 随着微电子技术的迅速发展以及集成电路规模不断提高，对电路性能的设计 要求越来越严格，这势必对用于大规模集成电路设计的EDA 工具提出越来越高的 要求。自1972 年美国加利福尼亚大学柏克莱分校电机工程和计算机科学系开发 的用于集成电路性能分析的电路模拟程序SPICE（Simulation Program with IC Emphasis）诞生以来，为适应现代微电子工业的发展，各种用于集成电路设计的 电路模拟分析工具不断涌现。HSPICE 是Meta-Software 公司为集成电路设计中 的稳态分析，瞬态分析和频域分析等电路性能的模拟分析而开发的一个商业化通 用电路模拟程序，它在柏克莱的SPICE（1972 年推出），MicroSim公司的PSPICE （1984 年推出）以及其它电路分析软件的基础上，又加入了一些新的功能，经 过不断的改进，目前已被许多公司、大学和研究开发机构广泛应用。HSPICE 可 与许多主要的EDA 设计工具，诸如Candence,Workview 等兼容，能提供许多重要 的针对集成电路性能的电路仿真和设计结果。采用HSPICE 软件可以在直流到高 于100MHz 的微波频率范围内对电路作精确的仿真、分析和优化。在实际应用中， HSPICE能提供关键性的电路模拟和设计方案，并且应用HSPICE进行电路模拟时， 其电路规模仅取决于用户计算机的实际存储器容量。 The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In additiOn, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
上传时间： 2013-10-18
上传用户：s363994250
介绍几种cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducing the advanced register based CPU architecture i.e., the MCS 251 microcontroller architecture. The register based CPU supports a 40-byte register file. In additiOn, the 8xC251SA/SB/SP/SQ microcontroller has 256-Kbyte expanded external code/data memory space and 64-Kbyte stack space. The new controller is also specially designed to execute C code efficiently. More importantly, the 8xC251SA/SB/SP/SQ maintains binary code compatibility with MCS 51 microcontrollers but at the same time allows the use of the powerful MCS 251 microcontroller instruction set, with many new 8, 16 and 32 bit instructions available. The 8xC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip data RAM options and is available in 16 Kbytes and 8 Kbytes of on-chip ROM/OTPROM or ROMless options.
标签： architecture introducin peripheral improves
上传时间： 2015-03-15
上传用户：ccclll
VC技术内幕第五版_English.The 6.0 release of Visual C++ shows Microsoft s continued focus on Internet technologies and COM, which are key components of the new Windows Distributed interNet Application Architecture (DNA). In additiOn to supporting these platform initiatives, Visual C++ 6.0 also adds an amazing number of productivity-boosting features such as Edit And Continue, IntelliSense, AutoComplete, and code tips. These features take Visual C++ to a new level. We have tried to make sure that this book keeps you up to speed on the latest technologies being introduced into Visual C++.
标签： Microsoft continued Internet English
上传时间： 2013-12-08
上传用户：lepoke
This firmware translates a PS/2 mouse to a USB mouse. The translator firmware is entirely interrupt driven (with the exception of sending the data via USB to the host.) An interrupt is generated when the PS/2 start bit is received, at which time the firmware will begin its receive routine. In additiOn to this interrupt, every 168ms a timer overflow interrupts the main program and implements one state of the mouse state machine. This state machine handles sending bytes to and translating bytes received from the PS/2 mouse automatically. All of this is done in the background while the main program runs in the foreground. The only operation that the main program implements is sending mouse data to the PC via USB.
标签： firmware mouse translates translator
上传时间： 2015-04-26
上传用户：cuiyashuo
Frequency Scale Conversion From f To f Scale frq2mel mel2frq mel The mel scale is based on the human perception of sinewave pitch. frq2erb erb2frq erb The erb scale is based on the equivalent rectangular bandwidths of the human ear. frq2midi midi2frq midi The midi standard specifies a numbering of semitones with middle C being 60. They can use the normal equal tempered scale or else the pythagorean scale of just intonation. They will in additiOn output note names in a character format.
标签： Scale Conversion Frequency mel
上传时间： 2015-06-07
上传用户：
YSS915 (KP2V2) is an LSI for processing Karaoke voice signals. This LSI has an A/D converter (1 channel) for the microphone echo, and a memory for the microphone echo and key control. These features allow achieving the functions needed for the Karaoke system by using only one LSI chip. As for the microphone echoes, many other types of echoes are available in additiOn to ordinary ones so that YSS915 is applicable to various uses. In additiOn to these Karaoke programs, YSS915 is able to provide the Movie & Music programs, with which the surround effect is applied to the movie and music sources for giving the users more enjoyment. YSS915 is pin compatible with and register compatible with YSS903 (KP2V).
标签： processing LSI converter Karaoke
上传时间： 2015-06-23
上传用户：lijianyu172
