On the design of an FPGA-Based OFDM modulator for IEEE 802.11a
标签： FPGA-Based modulator 802.11 design
上传时间： 2013-09-02
上传用户：zjwangyichao
protel s help on line
上传时间： 2013-09-18
上传用户：iswlkje
•Founded in Jan. 08, 2001 in Shanghai, China.•Fabless IDH focused on Analog & Mixed Signal Chip design & marketing •Over 100 IC introduced.•Over 200 OEM Customer worldwide•ISO-9000 Certified•Distribution Channel in Taiwan, China & Japan To achieve 100% customer satisfactionby producing the technically advanced product with the best quality, on-time delivery and service. Leverages on proprietary process and world-class engineering team to develop innovative & high quality analog solutions that add value to electronics equipment.
标签： Circuit Analog Design Porta
上传时间： 2013-10-24
上传用户：songnanhua
PCB设计问题集锦 问：PCB图中各种字符往往容易叠加在一起，或者相距很近，当板子布得很密时，情况更加严重。当我用Verify Design进行检查时，会产生错误，但这种错误可以忽略。往往这种错误很多，有几百个，将其他更重要的错误淹没了，如何使Verify Design会略掉这种错误，或者在众多的错误中快速找到重要的错误。 答：可以在颜色显示中将文字去掉,不显示后再检查;并记录错误数目。但一定要检查是否真正属于不需要的文字。 问： What’s mean of below warning:(6230,8330 L1) Latium Rule not checked: COMPONENT U26 component rule.答：这是有关制造方面的一个检查，您没有相关设定，所以可以不检查。 问： 怎样导出jop文件？答：应该是JOB文件吧？低版本的powerPCB与PADS使用JOB文件。现在只能输出ASC文件，方法如下STEP：FILE/EXPORT/选择一个asc名称/选择Select ALL/在Format下选择合适的版本/在Unit下选Current比较好/点击OK/完成然后在低版本的powerPCB与PADS产品中Import保存的ASC文件，再保存为JOB文件。 问： 怎样导入reu文件？答：在ECO与Design 工具盒中都可以进行，分别打开ECO与Design 工具盒，点击右边第2个图标就可以。 问： 为什么我在pad stacks中再设一个via:1(如附件）和默认的standardvi(如附件）在布线时V选择1，怎么布线时按add via不能添加进去这是怎么回事，因为有时要使用两种不同的过孔。答：PowerPCB中有多个VIA时需要在Design Rule下根据信号分别设置VIA的使用条件，如电源类只能用Standard VIA等等，这样操作时就比较方便。详细设置方法在PowerPCB软件通中有介绍。 问：为什么我把On-line DRC设置为prevent..移动元时就会弹出(图2),而你们教程中也是这样设置怎么不会呢?答：首先这不是错误,出现的原因是在数据中没有BOARD OUTLINE.您可以设置一个,但是不使用它作为CAM输出数据. 问：我用ctrl+c复制线时怎设置原点进行复制，ctrl+v粘帖时总是以最下面一点和最左边那一点为原点 答： 复制布线时与上面的MOVE MODE设置没有任何关系,需要在右键菜单中选择,这在PowerPCB软件通教程中有专门介绍. 问：用(图4)进行修改线时拉起时怎总是往左边拉起(图5)，不知有什么办法可以轻易想拉起左就左，右就右。答： 具体条件不明,请检查一下您的DESIGN GRID,是否太大了. 问： 好不容易拉起右边但是用(图6)修改线怎么改怎么下面都会有一条不能和在一起，而你教程里都会好好的(图8)答：这可能还是与您的GRID 设置有关,不过没有问题,您可以将不需要的那段线删除.最重要的是需要找到布线的感觉,每个软件都不相同,所以需要多练习。 问： 尊敬的老师:您好！这个图已经画好了，但我只对（如图1）一种的完全间距进行检查，怎么错误就那么多，不知怎么改进。请老师指点。这个图在附件中请老师帮看一下，如果还有什么问题请指出来，本人在改进。谢！！！！！答：请注意您的DRC SETUP窗口下的设置是错误的,现在选中的SAME NET是对相同NET进行检查,应该选择NET TO ALL.而不是SAME NET有关各项参数的含义请仔细阅读第5部教程. 问： U101元件已建好，但元件框的拐角处不知是否正确，请帮忙CHECK 答：元件框等可以通过修改编辑来完成。问： U102和U103元件没建完全，在自动建元件参数中有几个不明白：如：SOIC--》silk screen栏下spacing from pin与outdent from first pin对应U102和U103元件应写什么数值，还有这两个元件SILK怎么自动设置，以及SILK内有个圆圈怎么才能画得与该元件参数一致。 答：Spacing from pin指从PIN到SILK的Y方向的距离,outdent from first pin是第一PIN与SILK端点间的距离.请根据元件资料自己计算。
上传时间： 2013-10-07
上传用户：comer1123
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2013-10-15
上传用户：busterman
電子設備的 ON/OFF 按鈕給繫統設計師帶來了一組獨特的挑戰
上传时间： 2013-10-13
上传用户：18165383642
为解决传统可视倒车雷达视频字符叠加器结构复杂，可靠性差，成本高昂等问题，在可视倒车雷达设计中采用视频字符发生器芯片MAX7456。该芯片集成了所有用于产生用户定义OSD，并将其插入视频信号中所需的全部功能，仅需少量的外围阻容元件即可正常工作。给出了以MAX7456为核心的可视倒车雷达的软、硬件实现方案及设计实例。该方案具有电路结构简单、价格低廉、符合人体视觉习惯的特点。经实际装车测试，按该方案设计的可视倒车雷达视场清晰、提示字符醒目、工作可靠，可有效降低驾驶员倒车时的工作强度、减少倒车事故的发生。 Abstract: A new video and text generation chip，MAX7456，was used in the design of video parking sensor in order to simplify system structure，improve reliability and reduce cost. This chip included all the necessary functions to generate user-defined OSDs and to add them into the video signals. It could be put into work with addition of just a small number of resistances and capacitors. This paper provided software and hardware implementation solutions and design example based on the chip. The system had the characteristics of simplicity in circuit structure，lower cost，and comfort for the nature of human vision. Loading road test demonstrates high video and text display quality and reliable performance，which makes the driver easy to see backward and reduces chance of accidents.
上传时间： 2013-12-10
上传用户：qiaoyue
<Almost since the introduction of microcontrollers as electronic components there always has been an oscillatorcircuit on the device to make it work. From application point of view only some external components wererequired to make it work. However, to make sure that it will always work required more effort. This report is basedon feedback from the market from customers applying 8-bit mircrocontrollers.>
标签： oscillators X-tal bit mic
上传时间： 2013-11-12
上传用户：穿着衣服的大卫
PCB设计问题集锦 问：PCB图中各种字符往往容易叠加在一起，或者相距很近，当板子布得很密时，情况更加严重。当我用Verify Design进行检查时，会产生错误，但这种错误可以忽略。往往这种错误很多，有几百个，将其他更重要的错误淹没了，如何使Verify Design会略掉这种错误，或者在众多的错误中快速找到重要的错误。 答：可以在颜色显示中将文字去掉,不显示后再检查;并记录错误数目。但一定要检查是否真正属于不需要的文字。 问： What’s mean of below warning:(6230,8330 L1) Latium Rule not checked: COMPONENT U26 component rule.答：这是有关制造方面的一个检查，您没有相关设定，所以可以不检查。 问： 怎样导出jop文件？答：应该是JOB文件吧？低版本的powerPCB与PADS使用JOB文件。现在只能输出ASC文件，方法如下STEP：FILE/EXPORT/选择一个asc名称/选择Select ALL/在Format下选择合适的版本/在Unit下选Current比较好/点击OK/完成然后在低版本的powerPCB与PADS产品中Import保存的ASC文件，再保存为JOB文件。 问： 怎样导入reu文件？答：在ECO与Design 工具盒中都可以进行，分别打开ECO与Design 工具盒，点击右边第2个图标就可以。 问： 为什么我在pad stacks中再设一个via:1(如附件）和默认的standardvi(如附件）在布线时V选择1，怎么布线时按add via不能添加进去这是怎么回事，因为有时要使用两种不同的过孔。答：PowerPCB中有多个VIA时需要在Design Rule下根据信号分别设置VIA的使用条件，如电源类只能用Standard VIA等等，这样操作时就比较方便。详细设置方法在PowerPCB软件通中有介绍。 问：为什么我把On-line DRC设置为prevent..移动元时就会弹出(图2),而你们教程中也是这样设置怎么不会呢?答：首先这不是错误,出现的原因是在数据中没有BOARD OUTLINE.您可以设置一个,但是不使用它作为CAM输出数据. 问：我用ctrl+c复制线时怎设置原点进行复制，ctrl+v粘帖时总是以最下面一点和最左边那一点为原点 答： 复制布线时与上面的MOVE MODE设置没有任何关系,需要在右键菜单中选择,这在PowerPCB软件通教程中有专门介绍. 问：用(图4)进行修改线时拉起时怎总是往左边拉起(图5)，不知有什么办法可以轻易想拉起左就左，右就右。答： 具体条件不明,请检查一下您的DESIGN GRID,是否太大了. 问： 好不容易拉起右边但是用(图6)修改线怎么改怎么下面都会有一条不能和在一起，而你教程里都会好好的(图8)答：这可能还是与您的GRID 设置有关,不过没有问题,您可以将不需要的那段线删除.最重要的是需要找到布线的感觉,每个软件都不相同,所以需要多练习。 问： 尊敬的老师:您好！这个图已经画好了，但我只对（如图1）一种的完全间距进行检查，怎么错误就那么多，不知怎么改进。请老师指点。这个图在附件中请老师帮看一下，如果还有什么问题请指出来，本人在改进。谢！！！！！答：请注意您的DRC SETUP窗口下的设置是错误的,现在选中的SAME NET是对相同NET进行检查,应该选择NET TO ALL.而不是SAME NET有关各项参数的含义请仔细阅读第5部教程. 问： U101元件已建好，但元件框的拐角处不知是否正确，请帮忙CHECK 答：元件框等可以通过修改编辑来完成。问： U102和U103元件没建完全，在自动建元件参数中有几个不明白：如：SOIC--》silk screen栏下spacing from pin与outdent from first pin对应U102和U103元件应写什么数值，还有这两个元件SILK怎么自动设置，以及SILK内有个圆圈怎么才能画得与该元件参数一致。 答：Spacing from pin指从PIN到SILK的Y方向的距离,outdent from first pin是第一PIN与SILK端点间的距离.请根据元件资料自己计算。
上传时间： 2014-01-03
上传用户：Divine
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2014-01-24
上传用户：s363994250
