Use A/D channel scan mode in dspic programming
标签: programming channel dspic scan
上传时间: 2016-02-03
上传用户:bibirnovis
Designing Storage Area Networks - A Practical Reference For Implementing Fibre Channel And Ip Sans, Second Edition
标签: Implementing Designing Practical Reference
上传时间: 2016-02-08
上传用户:410805624
A 6 Channel PPM PIC code for 12F629 and 12F675,There are four examples here and they are work well for RC receiver.
标签: Channel 12F629 12F675 code
上传时间: 2013-12-23
上传用户:lindor
// 移频选频原理 //Fvco=[(P*B)+A]*Frefin/R //P=32 //loop filter 100k----prescribe //R=12.8M/100K=128---Parameter1 //Fvco=频点*2+170280 -1400 //B=Fvco/32-----------Parameter2 //A=Fvco-32*B
标签: 100 prescribe Frefin filter
上传时间: 2013-12-26
上传用户:dancnc
Rayleigh 信道仿真模型 参考"Autoregressive modeling for fading channel simulation", IEEE Transaction on Wireless Communications, July 2005.
标签: Autoregressive Transaction simulation Rayleigh
上传时间: 2016-03-15
上传用户:zwei41
Mahafza B.R, Elsherbeni A.Z. - MATLAB Simulations for Radar Systems Design - 2004 对于雷达系统设计师来说这是一本难得的宝典
标签: A.Z. Simulations Elsherbeni Mahafza
上传时间: 2016-03-20
上传用户:pinksun9
上以A R M 芯片为例,详细分析了在发生中断时如何实现中断现场的保护以及一 般嵌入式操作系统的多任务切换过程
上传时间: 2013-12-13
上传用户:BOBOniu
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN generation) 2) Modulator (RRC filter) 3) Demodulator (Matched Filter, RAKE receiver) 4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
标签: simulation baseband channel packet
上传时间: 2014-12-20
上传用户:ukuk
A paper on WiMax Simulation. The simulation include transmitter, receiver and channel model. AMC and MIMO are used.
标签: transmitter Simulation simulation and
上传时间: 2013-12-01
上传用户:金宜
This example provides a description of how to use a DMA channel to transfer a word data buffer from memory (Flash) to memory (RAM). The dedicated DMA channel is configured to transfer once a time a 32 word data buffer stored as constant in the Flash memory to another buffer in the RAM memory. The received data are stored in the DST_Buffer. The DMA channel transfer complete interrupt is enabled to generate an interrupt at the end of the buffer transfer. As soon as the transfer is completed an interrupt is generated and in the DMA channel interrupt routine the transfer complete interrupt pending bit is cleared. The data counter is stored before and after the transfer to show that all data has been transfered. TransferStatus gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED
标签: description provides transfer example
上传时间: 2016-04-24
上传用户:ecooo