ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
上传时间: 2013-11-12
上传用户:pans0ul
PCB设计问题集锦 问:PCB图中各种字符往往容易叠加在一起,或者相距很近,当板子布得很密时,情况更加严重。当我用Verify Design进行检查时,会产生错误,但这种错误可以忽略。往往这种错误很多,有几百个,将其他更重要的错误淹没了,如何使Verify Design会略掉这种错误,或者在众多的错误中快速找到重要的错误。 答:可以在颜色显示中将文字去掉,不显示后再检查;并记录错误数目。但一定要检查是否真正属于不需要的文字。 问: What’s mean of below warning:(6230,8330 L1) Latium Rule not checked: COMPONENT U26 component rule.答:这是有关制造方面的一个检查,您没有相关设定,所以可以不检查。 问: 怎样导出jop文件?答:应该是JOB文件吧?低版本的powerPCB与PADS使用JOB文件。现在只能输出ASC文件,方法如下STEP:FILE/EXPORT/选择一个asc名称/选择Select ALL/在Format下选择合适的版本/在Unit下选Current比较好/点击OK/完成然后在低版本的powerPCB与PADS产品中Import保存的ASC文件,再保存为JOB文件。 问: 怎样导入reu文件?答:在ECO与Design 工具盒中都可以进行,分别打开ECO与Design 工具盒,点击右边第2个图标就可以。 问: 为什么我在pad stacks中再设一个via:1(如附件)和默认的standardvi(如附件)在布线时V选择1,怎么布线时按add via不能添加进去这是怎么回事,因为有时要使用两种不同的过孔。答:PowerPCB中有多个VIA时需要在Design Rule下根据信号分别设置VIA的使用条件,如电源类只能用Standard VIA等等,这样操作时就比较方便。详细设置方法在PowerPCB软件通中有介绍。 问:为什么我把On-line DRC设置为prevent..移动元时就会弹出(图2),而你们教程中也是这样设置怎么不会呢?答:首先这不是错误,出现的原因是在数据中没有BOARD OUTLINE.您可以设置一个,但是不使用它作为CAM输出数据. 问:我用ctrl+c复制线时怎设置原点进行复制,ctrl+v粘帖时总是以最下面一点和最左边那一点为原点 答: 复制布线时与上面的MOVE MODE设置没有任何关系,需要在右键菜单中选择,这在PowerPCB软件通教程中有专门介绍. 问:用(图4)进行修改线时拉起时怎总是往左边拉起(图5),不知有什么办法可以轻易想拉起左就左,右就右。答: 具体条件不明,请检查一下您的DESIGN GRID,是否太大了. 问: 好不容易拉起右边但是用(图6)修改线怎么改怎么下面都会有一条不能和在一起,而你教程里都会好好的(图8)答:这可能还是与您的GRID 设置有关,不过没有问题,您可以将不需要的那段线删除.最重要的是需要找到布线的感觉,每个软件都不相同,所以需要多练习。 问: 尊敬的老师:您好!这个图已经画好了,但我只对(如图1)一种的完全间距进行检查,怎么错误就那么多,不知怎么改进。请老师指点。这个图在附件中请老师帮看一下,如果还有什么问题请指出来,本人在改进。谢!!!!!答:请注意您的DRC SETUP窗口下的设置是错误的,现在选中的SAME NET是对相同NET进行检查,应该选择NET TO ALL.而不是SAME NET有关各项参数的含义请仔细阅读第5部教程. 问: U101元件已建好,但元件框的拐角处不知是否正确,请帮忙CHECK 答:元件框等可以通过修改编辑来完成。问: U102和U103元件没建完全,在自动建元件参数中有几个不明白:如:SOIC--》silk screen栏下spacing from pin与outdent from first pin对应U102和U103元件应写什么数值,还有这两个元件SILK怎么自动设置,以及SILK内有个圆圈怎么才能画得与该元件参数一致。 答:Spacing from pin指从PIN到SILK的Y方向的距离,outdent from first pin是第一PIN与SILK端点间的距离.请根据元件资料自己计算。
上传时间: 2013-10-07
上传用户:comer1123
Specification: 输入信号:DC9-32V&AC100-240V 适用负载:电热负载,电感负载 控制方式:零点触发(Zero cross turn-on) 输入额定电压:AC 110-440±10% 输入额定电流:200-400A 使用频率:50/60Hz 使用环境:-10℃-50℃ 90%RH 冷却方式:风冷式
上传时间: 2013-11-14
上传用户:拔丝土豆
Specifying the right reference and applying it correctly isa more difficult task than one might first surmise, consideringthat references are only 2- or 3-terminal devices.Although the word “accuracy” is most often spoken inreference to references, it is dangerous to use this wordtoo freely because it can mean different things to differentpeople. Even more perplexing is the fact that a referenceclassified as a dog in one application is a panacea inanother. This application note will familiarize the readerwith the various aspects of reference “accuracy” andpresent some tips on extracting maximum performancefrom any reference.
标签: 电压基准
上传时间: 2013-10-15
上传用户:liuwei6419
AT89C2051驱动步进电机的电路和源码:AT89C2051驱动步进电机的电路和源码 程序:stepper.c stepper.hex/* * STEPPER.C * sweeping stepper's rotor cw and cww 400 steps * Copyright (c) 1999 by W.Sirichote */#i nclude c:\mc5151io.h /* include i/o header file */ #i nclude c:\mc5151reg.hregister unsigned char j,flag1,temp; register unsigned int cw_n,ccw_n;unsigned char step[8]={0x80,0xc0,0x40,0x60,0x20,0x30,0x10,0x90} #define n 400/* flag1 mask byte 0x01 run cw() 0x02 run ccw() */main(){ flag1=0; serinit(9600); disable(); /* no need timer interrupt */ cw_n = n; /* initial step number for cw */ flag1 |=0x01; /* initial enable cw() */while(1){ { tick_wait(); /* wait for 10ms elapsed */energize(); /* round-robin execution the following tasks every 10ms */ cw(); ccw(); } }}cw(){ if((flag1&0x01)!=0) { cw_n--; /* decrement cw step number */ if (cw_n !=0) j++; /* if not zero increment index j */ else {flag1&=~0x01; /* disable cw() execution */ ccw_n = n; /* reload step number to ccw counter */ flag1 |=0x02; /* enable cww() execution */ } }
上传时间: 2013-11-21
上传用户:boyaboy
PCB设计问题集锦 问:PCB图中各种字符往往容易叠加在一起,或者相距很近,当板子布得很密时,情况更加严重。当我用Verify Design进行检查时,会产生错误,但这种错误可以忽略。往往这种错误很多,有几百个,将其他更重要的错误淹没了,如何使Verify Design会略掉这种错误,或者在众多的错误中快速找到重要的错误。 答:可以在颜色显示中将文字去掉,不显示后再检查;并记录错误数目。但一定要检查是否真正属于不需要的文字。 问: What’s mean of below warning:(6230,8330 L1) Latium Rule not checked: COMPONENT U26 component rule.答:这是有关制造方面的一个检查,您没有相关设定,所以可以不检查。 问: 怎样导出jop文件?答:应该是JOB文件吧?低版本的powerPCB与PADS使用JOB文件。现在只能输出ASC文件,方法如下STEP:FILE/EXPORT/选择一个asc名称/选择Select ALL/在Format下选择合适的版本/在Unit下选Current比较好/点击OK/完成然后在低版本的powerPCB与PADS产品中Import保存的ASC文件,再保存为JOB文件。 问: 怎样导入reu文件?答:在ECO与Design 工具盒中都可以进行,分别打开ECO与Design 工具盒,点击右边第2个图标就可以。 问: 为什么我在pad stacks中再设一个via:1(如附件)和默认的standardvi(如附件)在布线时V选择1,怎么布线时按add via不能添加进去这是怎么回事,因为有时要使用两种不同的过孔。答:PowerPCB中有多个VIA时需要在Design Rule下根据信号分别设置VIA的使用条件,如电源类只能用Standard VIA等等,这样操作时就比较方便。详细设置方法在PowerPCB软件通中有介绍。 问:为什么我把On-line DRC设置为prevent..移动元时就会弹出(图2),而你们教程中也是这样设置怎么不会呢?答:首先这不是错误,出现的原因是在数据中没有BOARD OUTLINE.您可以设置一个,但是不使用它作为CAM输出数据. 问:我用ctrl+c复制线时怎设置原点进行复制,ctrl+v粘帖时总是以最下面一点和最左边那一点为原点 答: 复制布线时与上面的MOVE MODE设置没有任何关系,需要在右键菜单中选择,这在PowerPCB软件通教程中有专门介绍. 问:用(图4)进行修改线时拉起时怎总是往左边拉起(图5),不知有什么办法可以轻易想拉起左就左,右就右。答: 具体条件不明,请检查一下您的DESIGN GRID,是否太大了. 问: 好不容易拉起右边但是用(图6)修改线怎么改怎么下面都会有一条不能和在一起,而你教程里都会好好的(图8)答:这可能还是与您的GRID 设置有关,不过没有问题,您可以将不需要的那段线删除.最重要的是需要找到布线的感觉,每个软件都不相同,所以需要多练习。 问: 尊敬的老师:您好!这个图已经画好了,但我只对(如图1)一种的完全间距进行检查,怎么错误就那么多,不知怎么改进。请老师指点。这个图在附件中请老师帮看一下,如果还有什么问题请指出来,本人在改进。谢!!!!!答:请注意您的DRC SETUP窗口下的设置是错误的,现在选中的SAME NET是对相同NET进行检查,应该选择NET TO ALL.而不是SAME NET有关各项参数的含义请仔细阅读第5部教程. 问: U101元件已建好,但元件框的拐角处不知是否正确,请帮忙CHECK 答:元件框等可以通过修改编辑来完成。问: U102和U103元件没建完全,在自动建元件参数中有几个不明白:如:SOIC--》silk screen栏下spacing from pin与outdent from first pin对应U102和U103元件应写什么数值,还有这两个元件SILK怎么自动设置,以及SILK内有个圆圈怎么才能画得与该元件参数一致。 答:Spacing from pin指从PIN到SILK的Y方向的距离,outdent from first pin是第一PIN与SILK端点间的距离.请根据元件资料自己计算。
上传时间: 2014-01-03
上传用户:Divine
This hands-on, one-stop guide delivers the focused, streamlined direction you need to get your Web solutions up and running quickly. Zero in on key ASP.NET configuration details and techniques using quick-reference tables, lists, coding and more.
标签: streamlined direction hands-on delivers
上传时间: 2015-01-11
上传用户:Thuan
This program will ask how many numbers you want to find the average of, then it will allow you to enter your numbers(yes they can even be decimals) then it will calculate the mean, median, mode and range of what you enter.
上传时间: 2015-03-23
上传用户:skhlm
This a Bayesian ICA algorithm for the linear instantaneous mixing model with additive Gaussian noise [1]. The inference problem is solved by ML-II, i.e. the sources are found by integration over the source posterior and the noise covariance and mixing matrix are found by maximization of the marginal likelihood [1]. The sufficient statistics are estimated by either variational mean field theory with the linear response correction or by adaptive TAP mean field theory [2,3]. The mean field equations are solved by a belief propagation method [4] or sequential iteration. The computational complexity is N M^3, where N is the number of time samples and M the number of sources.
标签: instantaneous algorithm Bayesian Gaussian
上传时间: 2013-12-19
上传用户:jjj0202
The goal with this project was to make it possible for almost any mobile-phone to use ICQ and be able to communicate with other users! One other goal with this project was to lower the GPRS-traffic in the phone and make the ICQ-ing cheaper. A third goal was to make this service as easy to log-in to as possible. Anyone tried to fill a log-in screen with a WAP-browser should know what I mean. With Wapmess all you have to do is to write your login-url ONCE and then bookmark it in your phone, to make it available fast. :)
标签: mobile-phone possible project almost
上传时间: 2015-04-08
上传用户:xiaodu1124