Xilinx-XUPV

基于Xilinx+FPGA的OFDM通信系统基带设计-程序

《基于Xilinx FPGA的OFDM通信系统基带设计》附带的代码

标签： Xilinx FPGA OFDM 通信系统

上传时间： 2013-12-21

上传用户：王庆才
Xilinx-Spartan6 FPGA实现MultiBoot

通过Xilinx Spartan-6 FPGA 的Multiboot特性,允许用户一次将多个配置文件下载入Flash中,根据不同时刻的需求,在不掉电重启的情况下,从中选择一个来重配置FPGA,实现不同功能,提高器件利用率,增加系统安全性,降低系统成本。

标签： Xilinx-Spartan MultiBoot FPGA

上传时间： 2013-10-26

上传用户：wpwpwlxwlx
WP374 Xilinx FPGA的部分重配置

WP374 Xilinx FPGA的部分重配置

标签： Xilinx FPGA 374 WP

上传时间： 2013-11-03

上传用户：文993
XAPP503-针对Xilinx器件的SVF和XSVF文件格式

This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded programming applications

标签： Xilinx XAPP XSVF 503

上传时间： 2015-01-02

上传用户：时代将军
XAPP944 - 将Xilinx CoolRunner-II CPLD用作数据流开关

This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources

标签： CoolRunner-II Xilinx XAPP CPLD

上传时间： 2013-12-16

上传用户：qwer0574
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案

WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮点DSP算法实现方案： High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs

标签： Xilinx FPGA 409 DSP

上传时间： 2013-10-21

上传用户：huql11633
基于Xilinx FPGA的双输出DC/DC转换器解决方案

Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.

标签： Xilinx FPGA DC 输出

上传时间： 2013-10-22

上传用户：aeiouetla
WP312-Xilinx新一代28nm FPGA技术简介

Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.

标签： Xilinx FPGA 312 WP

上传时间： 2013-12-07

上传用户：bruce
xilinx Zynq-7000 EPP产品简介

The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.

标签： xilinx Zynq 7000 EPP

上传时间： 2013-10-09

上传用户：evil
XAPP058 -利用嵌入式微控制器实现Xilinx系统编程

Xilinx 高性能 CPLD、FPGA 和配置 PROM 系列具备在系统可编程性、可靠的引脚锁定以及JTAG 边界扫描测试功能。此强大的功能组合允许设计人员在进行重大更改时，仍能保留原始的器件引脚，从而避免重组 PC 板。通过利用嵌入式控制器从板载 RAM 或 EPROM 对这些CPLD 和 FPGA 编程，设计人员可轻松升级、修改和测试设计，即使在现场也是如此。

标签： Xilinx XAPP 058 嵌入式

上传时间： 2013-11-03

上传用户：dongbaobao