VHDL SDRAM

cpld的入门交流：CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言

cpld的入门交流：CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言遍的

标签： cpld CPLD VHDL 交流

上传时间： 2013-09-06

上传用户：blacklee
LED\\LCD控制，多种接口等十几个VHDL经典程序

集中了十几个vhdl经典程序,如lcd,led控制程序和多种接口程序

标签： VHDL LED LCD 控制

上传时间： 2013-09-06

上传用户：Huge_Brother
用VHDL语言在CPLD上实现串行通信

用VHDL语言在CPLD上实现串行通信

标签： VHDL CPLD 语言串行通信

上传时间： 2013-09-06

上传用户：q3290766
VHDL实现：单片机与FPGA接口通信源文件

程序主要用硬件描述语言（VHDL）实现：\r\n单片机与FPGA接口通信的问题

标签： VHDL FPGA 单片机接口通信

上传时间： 2013-09-06

上传用户：ddddddos
VHDL硬件语言编写的曼彻斯特码的解码程序

此曼彻斯特码的解码程序是采用VHDL硬件语言编写的。

标签： VHDL 硬件曼彻斯特语言

上传时间： 2013-09-06

上传用户：zhouli
用vhdl编写的基于fpga的数字频率计程序算法

用vhdl编写的基于fpga的数字频率计程序算法

标签： vhdl fpga 编写数字频率计

上传时间： 2013-09-07

上传用户：chfanjiang
US Navy VHDL Modelling Guide

This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.

标签： Modelling Guide Navy VHDL

上传时间： 2014-12-23

上传用户：xinhaoshan2016
PLD Programming Using VHDL

本文详细讨论了VHDL语句对PLD设计的影响和设计经验，经典文章，值得仔细阅读消化。,PLD Programming Using VHDL

标签： Programming Using VHDL PLD

上传时间： 2013-11-17

上传用户：teddysha
VHDL,Verilog,System verilog比较

本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

标签： Verilog verilog System VHDL

上传时间： 2013-10-16

上传用户：牛布牛
多功能数字钟的VHDL设计

多功能数字钟的VHDL设计

标签： VHDL 多功能数字

上传时间： 2013-10-29

上传用户：swz13842860183