VHDL 计算器

VHDL,Verilog,System verilog比较

本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

标签： Verilog verilog System VHDL

上传时间： 2014-03-03

上传用户：zhtzht
基于CPLD的VHDL语言数字钟(含秒表)设计

利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。

标签： CPLD VHDL 语言数字

上传时间： 2013-10-24

上传用户：古谷仁美
ZBT SRAM控制器参考设计,xilinx提供VHDL代码

ZBT SRAM控制器参考设计,xilinx提供VHDL代码 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.

标签： xilinx SRAM VHDL ZBT

上传时间： 2013-10-25

上传用户：peterli123456
USB接口控制器参考设计,xilinx提供VHDL代码 us

USB接口控制器参考设计,xilinx提供VHDL代码 usb xilinx vhdl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

标签： xilinx VHDL USB us

上传时间： 2013-10-29

上传用户：zhouchang199
ref sdr sdram vhdl代码

ref-sdr-sdram-vhdl代码 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.

标签： sdram vhdl ref sdr

上传时间： 2013-10-23

上传用户：半熟1994
UART 4 UART参考设计，Xilinx提供VHDL代码

UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.

标签： UART Xilinx VHDL 参考设计

上传时间： 2013-11-02

上传用户：18862121743
各种功能的计数器实例（VHDL源代码）

各种功能的计数器实例（VHDL源代码）:

标签： VHDL 计数器源代码

上传时间： 2013-10-19

上传用户：xanxuan
各种功能的计数器实例（VHDL源代码）

各种功能的计数器实例（VHDL源代码）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;

标签： VHDL 计数器源代码

上传时间： 2013-10-09

上传用户：松毓336
DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。

DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。

标签： TESTBENCH VERILOG VHDL DES

上传时间： 2015-01-04

上传用户：songyue1991
一个多功能计算器calc

一个多功能计算器calc，包含了代数运算、矩阵运算等功能

标签： calc 多功能计算器

上传时间： 2013-12-09

上传用户：athjac