16位计数器的设计，这里是实现上述功能的VHDL源程序，供大家学习和讨论。\r\n
上传时间： 2013-09-05
上传用户：weiwolkt
cpld的入门交流：CPLD的跑馬燈一个简易型cpld试验电路用VHDL语言遍的
上传时间： 2013-09-06
上传用户：blacklee
集中了十几个vhdl经典程序,如lcd,led控制程序和多种接口程序
上传时间： 2013-09-06
上传用户：Huge_Brother
用VHDL语言在CPLD上实现串行通信
上传时间： 2013-09-06
上传用户：q3290766
程序主要用硬件描述语言（VHDL）实现：\r\n单片机与FPGA接口通信的问题
上传时间： 2013-09-06
上传用户：ddddddos
此曼彻斯特码的解码程序是采用VHDL硬件语言编写的。
上传时间： 2013-09-06
上传用户：zhouli
用vhdl编写的基于fpga的数字频率计程序算法
上传时间： 2013-09-07
上传用户：chfanjiang
这是一个简单的计算器，可以简单的计算整数的加减．
标签： 计算器
上传时间： 2013-09-20
上传用户：mnacyf
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上传时间： 2014-12-23
上传用户：xinhaoshan2016
本文详细讨论了VHDL语句对PLD设计的影响和设计经验，经典文章，值得仔细阅读消化。,PLD Programming Using VHDL
标签： Programming Using VHDL PLD
上传时间： 2013-11-17
上传用户：teddysha
