This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上传时间： 2014-01-24
上传用户：s363994250
Accurate measurement of the third order intercept pointfor low distortion IC products such as the LT5514 requirescertain precautions to be observed in the test setup andtesting procedure. The LT5514 linearity performance ishigh enough to push the test equipment and test set-up totheir limits. A method for accurate measurement of thirdorder intermodulation products, IM3, with standard testequipment is outlined below.It is also important to correctly interpret the LT5514specification with respect to ROUT, and the impact ofdemo-board transmission-line termination loss whenevaluating the linearity performance, as explained in theLT5514 Datasheet and in Note 1 of this document.
上传时间： 2013-11-14
上传用户：l254587896
USB TO RS232 RS485 UART转接板电路原理图
上传时间： 2013-10-22
上传用户：macarco
program to trasmit data to a TI92 with the TI Graph-Link
标签： Graph-Link program trasmit data
上传时间： 2015-01-03
上传用户：youke111
Transfer Files to and from an FTP Server
标签： Transfer Server Files from
上传时间： 2013-12-17
上传用户：jing911003
Mastering Oracle SQL By Alan Beaulieu, Sanjay Mishra Publisher : O Reilly Pub Date : April 2002 ISBN : 0-596-00129-0 Pages : 336 Slots : 1
标签： Mastering Publisher Beaulieu Oracle
上传时间： 2014-01-15
上传用户：Yukiseop
This book introduces embedded systems to C and C++ programmers. Topics include testing memory devices, writing and erasing Flash memory, verifying nonvolatile memory contents, controlling on-chip peripherals, device driver design and implementation, optimizing embedded code for size and speed, and making the most of C++ without a performance penalty. Pages : 336 Slots : 1
标签： programmers introduces embedded include
上传时间： 2013-12-10
上传用户：shizhanincc
CGAL is a collaborative effort of several sites in Europe and Israel. The goal is to make the most important of the solutions and methods developed in computational geometry available to users in industry and academia in a C++ library. The goal is to provide easy access to useful, reliable geometric algorithms
标签： collaborative several Europe Israel
上传时间： 2015-01-09
上传用户：refent
source code to compute the visibility polygon of a point in a polygon.
标签： polygon visibility compute source
上传时间： 2015-01-09
上传用户：wpt
hex file to bin file convert tool
上传时间： 2014-01-20
上传用户：moerwang
